Silence unused function warning when graphviz is not available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152346 91177308-0d34-0410-b5e6-96231b3b80d8
Cache MBB->begin. It's possible the scheduler / bundler may change MBB->begin().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152356 91177308-0d34-0410-b5e6-96231b3b80d8
Added TargetPassConfig::enablePass

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152359 91177308-0d34-0410-b5e6-96231b3b80d8
misched: allow the default scheduler to be one chosen by the target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152360 91177308-0d34-0410-b5e6-96231b3b80d8
Fix a regression from r147481.

Original commit message from r147481:
DAGCombine for transforming 128->256 casts into a vmovaps, rather
then a vxorps + vinsertf128 pair if the original vector came from a load.

Fix:
Unaligned loads need to generate a vmovups.
rdar://10974078



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152366 91177308-0d34-0410-b5e6-96231b3b80d8
Undo a previous restriction on the inline cost calculation which Nick
introduced. Specifically, there are cost reductions for all
constant-operand icmp instructions against an alloca, regardless of
whether the alloca will in fact be elligible for SROA. That means we
don't want to abort the icmp reduction computation when we abort the
SROA reduction computation. That in turn frees us from the need to keep
a separate worklist and defer the ICmp calculations.

Use this new-found freedom and some judicious function boundaries to
factor the innards of computing the cost factor of any given instruction
out of the loop over the instructions and into static helper functions.
This greatly simplifies the code, and hopefully makes it more clear what
is happening here.

Reviewed by Eric Christopher. There is some concern that we'd like to
ensure this doesn't get out of hand, and I plan to benchmark the effects
of this change over the next few days along with some further fixes to
the inline cost.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152368 91177308-0d34-0410-b5e6-96231b3b80d8
Fix a silly restriction on the fast-path for hash_combine_range. This
caused several clients to select the slow variation. =[ This is extra
annoying because we don't have any realistic way of testing this -- by
design, these two functions *must* compute the same value.

Found while inspecting the output of some benchmarks I'm working on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152369 91177308-0d34-0410-b5e6-96231b3b80d8
revert 152356: verify misched changes using -misched=shuffle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152373 91177308-0d34-0410-b5e6-96231b3b80d8
misched comments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152374 91177308-0d34-0410-b5e6-96231b3b80d8
misched interface: rename Begin/End to RegionBegin/RegionEnd since they are not private.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152382 91177308-0d34-0410-b5e6-96231b3b80d8
Fix undefined behavior in the Mips backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152390 91177308-0d34-0410-b5e6-96231b3b80d8
Use uint16_t to store opcodes in static tables in X86 backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152391 91177308-0d34-0410-b5e6-96231b3b80d8
misched: handle scheduling region boundaries nicely.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152393 91177308-0d34-0410-b5e6-96231b3b80d8
[llvm.py] Initial skeleton for Python LLVM bindings

This contains a semi-functional skeleton for the implementation of the
LLVM bindings for Python.

The API for the Object.h interface is roughly designed but not
implemented. MemoryBufferRef is implemented and actually appears to
work!

The ObjectFile unit test fails with a segmentation fault because the
LLVM library isn't being properly initialized. The build system doesn't
know about this code yet, so no alerts should fire.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152397 91177308-0d34-0410-b5e6-96231b3b80d8
Factor out the analysis of addition and subtraction in ComputeMaskedBits. Reuse
it to analyze extractvalue(llvm.[us](add|sub).with.overflow.*) intrinsics!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152398 91177308-0d34-0410-b5e6-96231b3b80d8
Add support for r600 (AMD GPUs HD2XXX - HD6XXX) target triplet.

Patch by Tom Stellard!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152400 91177308-0d34-0410-b5e6-96231b3b80d8
Eliminate switch cases that can never match, for example removes all
negative switch cases if the branch condition is known to be positive.
Inspired by a recent improvement to GCC's VRP.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152405 91177308-0d34-0410-b5e6-96231b3b80d8
test/MC/X86/lit.local.cfg: Fix up to detect 'X86' in targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152406 91177308-0d34-0410-b5e6-96231b3b80d8
TableGen/CodeEmitterGen.cpp: Fix an expression of generating bitmask.

~0U might be i32 on 32-bit hosts, then (uint64_t)~0U might not be expected as (i64)0xFFFFFFFF_FFFFFFFF, but as (i64)0x00000000_FFFFFFFF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152407 91177308-0d34-0410-b5e6-96231b3b80d8
[Support] Drop verbose _ATTRIBUTE from LLVM_ATTRIBUTE_{READONLY,READNONE} macro
names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152413 91177308-0d34-0410-b5e6-96231b3b80d8