TI814X: Add support for detecting Cent PG3.0

This patch enable support for detecting ti8148
version 3.0 silicon.

Signed-off-by: Raj, Deepu <deepu.raj@ti.com>
Signed-off-by: Nageswari Srinivasan <nageswari@ti.com>
TI81XX: Enable support for D-cache and MMU for TI81XX

This patch enables the supprot for D-cache with MMU
identical mapping. I-cache is enabled by default in
the start.S but D-cache is not enable by default and it
can be manage by the set of following apis.
	dcache_enable()
	dcache_disable()
	invalidate_dcache_range()
	flush_dcache_rage()

- D-cache operations supported:
        - Invalidate entire D-cache
        - Invalidate D-cache range
        - Flush(clean & invalidate) entire D-cache
        - Flush D-cache range

This patch is basesd on the following patches for MMU
support and cache maintance for armv7

http://git.denx.de/?p=u-boot.git;a=commitdiff;h=880eff5cfb9df6f0855f4e48affd349ca64692e9
        ARM: cp15: setup mmu and enable dcache

http://git.denx.de/?p=u-boot.git;a=commitdiff;h=2c451f7831208741d0ff7ca6046cffcd9ee49def
        Add a framework for layered cache maintenance
        separate out SOC specific outer cache maintenance from
        maintenance of caches known to CPU

Signed-off-by: Raj, Deepu <deepu.raj@ti.com>
TI81XX: cpsw: move descriptors to bd ram

Moving the desciptor memory space to bd ram to support d-cache

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
TI81XX: cpsw: enable d-cache support for cpsw driver

Thispatch enables D-cache support for cpsw driver

* Increase PKTALIGN from 32 to 64 to make packet buffer memory 64 bytes align
* d-cache flush and d-cache validata before send and receive a packet respectively

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
TI814X: Fixed USB PLL divider value for PG3.0

This patch fixed the divider values used for
UART in the USB PLL config.The divider selection
is done based on the runtime PG value.

Signed-off-by: Raj, Deepu <deepu.raj@ti.com>
ti814x: Write to SMA0 register only when device earlier than PG2.0

PG2.x and onwards devices do not need write to this register.

Signed-off-by: Hemant Pedanekar <hemantp@ti.com>
ti81xx: pcie: Add support for  PCIe boot mode for TI813X

Reuses TI814X code by including the build for board/ti/ti8148/pcie.c as most of
the code is common. As a side effect, the boot pin based BAR size configuration
is exactly same as TI814X.

Note that similar to TI814X/TI816X, two build configurations are added to
support 32-bit and 64-bit boot modes.
	32-bit --> ti813x_evm_min_pcie_32
	64-bit --> ti813x_evm_min_pcie_64

The boot medium is SPI.

Signed-off-by: Hemant Pedanekar <hemantp@ti.com>
drivers: net: cpsw: halt cpsw properly to stop receiving properly

During cpsw driver halt, cpdma and cpsw must be stopped from processing
network packets to ensure that hardware doesn't modify any DDR data where
kernel may have its own data structures

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
drivers: net: cpsw: net_send dcache flush usage bug fix

In net_send dcache flush is done on buffer variable, which can be same packet
pointer or it can be NULL when there is no tx desc in cpdma.
Fixed the issue by making dcache_flush on packet pointer.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
drivers: net: cpsw: fix compier warning with d-cache usage

Fix compier warning with d-cache api usage as there is a data type mismatch

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
TI811X: NOR XIP boot support for ti811x

TI811X EVM Ethernet and NOR can not be used at
same time due to the Muxing of GPMC addr lines
and EMAC_0/1. This patch removes the ETH support
and just enabling the NOR XIP boot support.

Signed-off-by: Raj, Deepu <deepu.raj@ti.com>
TI811X:  fixed the PG version print on ti811x

This patch fixes the bug in the PG version printing
on TI811X and TI813X platforms.

Signed-off-by: Raj, Deepu <deepu.raj@ti.com>
TI816X: updated the MAIN PLL N values for ti8168

This patch updates the MAIN PLL N divider values to
fix the pll locking issue on found during the silicon
characterization.

Signed-off-by: Raj, Deepu <deepu.raj@ti.com>
TI811X: U-boot boot logo updated for TI811x

u-boot boot logo is updated to product name
TI811x from the internal name J5Eco

Signed-off-by: Raj, Deepu <deepu.raj@ti.com>
ti8148: mmc: use gpio pin for card detection

Hook up the relevant GPIO pin to handle the card detect
functionality on ti8148 platform.

Signed-off-by: Saxena, Parth <parth.saxena@ti.com>
ti811x: mmc: use gpio pin for card detection

Hook up the relevant GPIO pin to handle the card detect
functionality on ti811x platform.

Signed-off-by: Saxena, Parth <parth.saxena@ti.com>
ti811x: mmc: use gpio pin for write protection

Hook up the relevant GPIO pin to handle the write protect
functionality on ti811x platform.

Signed-off-by: Saxena, Parth <parth.saxena@ti.com>
drivers: net: cpsw: optimize cpsw_send to increase network performance

Before submitting packets to cpdma, phy status is updated on every packet
which leads to delay in packet send intern reduces the Ethernet performance.
Checking mdio status for each packet will reduce timetaken to send a packet
and there by increasing the Ethernet performance.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
TI814X: Fixes the ADPLL_J dco freq selection

This patch added the support for selecting the
DCO_FREQ range (HS1/H2) bases on the CLKDCOout
value getting configured for each PLL.

Signed-off-by: Raj, Deepu <deepu.raj@ti.com>
TI8148: Added support for DDR3 byte-wise leveling

This patch enables support for the DDR3 byte-wise
software leveling configurations.ddr_def_ti814x.h
contains the macros for each byte lane values.

Signed-off-by: Raj, Deepu <deepu.raj@ti.com>