r600g: fix printf warning
r600g: remove unused function
glsl: Generate compile errors for explicit blend indices < 0 or > 1.

According to the GLSL 4.30 specification, this is a compile time error.
Earlier specifications don't specify a behavior, but since 0 and 1 are
the only valid indices for dual source blending, it makes sense to
generate the error.

Fixes (the fixed version of) piglit's layout-12.frag.

NOTE: This is a candidate for the 9.0 branch.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
i965: Remove incorrect comment above opt_algebraic.

The comment was cut-and-pasted from propagate_constants(), and had no
relation at all to opt_algebraic().
radeonsi: Handle NULL sampler states.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
radeonsi: Texture border colour fixes.

* Handle arbitrary border colours.
* Use correct packing format for detecting special border colours.

Fixes piglit tex-border-1 and probably many other tests using border colours.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
r600g: avoid GPU doing constant preload from random address

Previous command stream might have set any of the constant buffer
and the previous address might no longer be valid thus GPU might
preload constant from random invalid address and possibly triggering
lockup.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
radeon/llvm: Add SHADER_TYPE instruction

This allows the program to specify the type of shader being compiled
(e.g. PXEL, VERTEX, etc.)

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
radeonsi: Pass shader type to the compiler

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
radeonsi: Add missing interpolation mode to check for enabled modes

At least one interpolation mode must be enable, but the code that checks
this was not checking for perspective center.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
radeonsi: Move interpolation mode check into the compiler

The compiler needs to know which interpolation modes are enabled, so
it knows which values will be preloaded into the VGPRs.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
radeon/llvm: Coding style fixes

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
radeonsi: Handle position input parameter for pixel shaders v2

v2:
  - Don't increment ninterp or set any of the have_* flags for
    TGSI_SEMANTIC_POSITION

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
radeon/llvm: Ignore special registers when calculating reg count

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
radeon/llvm: Add register encoding for VCC

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
radeon/llvm: Assert if we try to encode an unknown register

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
radeon/llvm: Fix operand order of V_CNDMASK in custom inserter

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
i965/blorp: Fix narrowing warnings.

Blorp has to convert rectangle coordinates from integers to floats in
order to send them down the GPU pipeline.  Recent versions of GCC
issue a warning for this, since a float is not capable of precisely
representing all possible 32-bit integer values.  Suppress the warning
with an explicit type cast in the case of blorp, since rectangle
coordinates will never be large enough to cause a loss of precision.
mesa/msaa: Allow X and Y flips in multisampled blits.

From the GL 4.3 spec, section 18.3.1 "Blitting Pixel Rectangles":

    If SAMPLE_BUFFERS for either the read framebuffer or draw
    framebuffer is greater than zero, no copy is performed and an
    INVALID_OPERATION error is generated if the dimensions of the
    source and destination rectangles provided to BlitFramebuffer are
    not identical, or if the formats of the read and draw framebuffers
    are not identical.

It is not clear from the spec whether "dimensions" should mean both
sign and magnitude, or just magnitude.

Previously, Mesa interpreted "dimensions" as meaning both sign and
magnitude, so any multisampled blit that attempted to flip the image
in the X and/or Y direction would fail.

However, Y flips are likely to be commonplace in OpenGL applications
that have been ported from DirectX applications, as a result of the
fact that DirectX and OpenGL differ in their orientation of the Y
axis.  Furthermore, at least one commercial driver (nVidia) permits Y
filps, and L4D2 relies on them being permitted.  So it seems prudent
for Mesa to permit them.

This patch changes Mesa to allow both X and Y flips, since there is no
language in the spec to indicate that X and Y flips should be treated
differently.

NOTE: This is a candidate for stable release branches.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
i965/gen6+: Adjust stencil buffer size after computing miptree layout.

Since Gen6+ stencil buffers use W-tiling (a tiling arrangement which
drm and the kernel are not aware of) we need to round up the width and
height of a stencil buffer to multiples of the W-tile size (64x64)
before allocating a stencil buffer.  Previously, we rounded up the
size of the base miplevel, and then computed the miptree layout based
on the rounded up size.  This was incorrect, because it meant that the
total size of the miptree would not be properly W-tile aligned, and
therefore we would not always allocate enough pages.

(Note: even though the GL API doesn't allow creation of mipmapped
stencil textures, it does allow mipmapping of a combined depth/stencil
texture, and on Gen6+, a combined depth/stencil texture is internally
implemented as a pair of separate depth and stencil buffers.)

For example, on Sandy Bridge, when allocating a mipmapped stencil
texture of size 128x128, we would first round up to the nearest
multiple of 64x64 (causing no change to the size), and then compute
the miptree layout (whose size worked out to 128x196).  Then we would
request an allocation of 128*196 bytes (6.125 pages), causing 7 pages
to be allocated to the texture.  However, the texture needs 8 pages,
since each W-tile occupies a page, and it takes 2 W-tiles to cover a
width of 128 and 4 W-tiles to cover a height of 196.

This patch changes the order of operations so that the miptree layout
is computed first and then the total size of the miptree is rounded up
to be W-tile aligned.

NOTE: This is a candidate for stable release branches.

Reviewed-by: Eric Anholt <eric@anholt.net>