Disable FSync by default
omap/opp4xxxx: Enable SGX OPP3 (GPU Overclocking)

Originally by Michael Huang aka coolbho3k

Michael Huang <coolbho3k.xxx.xx>
(cherry picked from commit 3ce9a87b04011deea480a31fa691b37e91e8fb05)
opp4xxx: enable OPPNitro speed bin
(cherry picked from commit aea8fa06f1d5120c073b5dc3224c80faa785689f)

Conflicts:

	arch/arm/mach-omap2/opp4xxx_data.c
OPP4xxx: Add compile time undervolt option
(cherry picked from commit 6a819a59d732ab01aa170bc89f549dd5dc3aeaae)
Overclock: clean up and fix derpage

Add OMAP NitroSB, moved 1.35GHz to use the new entry
Add GPU overclock compilation switch
Adjust Undervolt values to be 10% across the board
Allow undervolt for IVA DSP as well
Fix GPU overclock derp from Michael Huang
(cherry picked from commit de13fd33d4efb51283825327ba1adde9e92a0f48)
OPP4xxx: Increase voltage values from 90% of stock to 95% for stability
(cherry picked from commit 7556ac6b8d4d42f500c7d37d27008aaf29884346)
OMAP4: HSI: changed Fclk to 192Mhz for OPP100

HSI RX and TX bit rates depend on HSI Functional clock and cannot be higher
than Fclk.
Allowed higher HSI throughputs by enabling 192MHz@OPP100.

Change-Id: I274f0860d48ec79a1331366b8866f883ae372d2f
Signed-off-by: Djamil Elaidi <d-elaidi@ti.com>
(cherry picked from commit 01934d2b882e612c93104700fbd16bce1e770075)
OMAP44xx: Add OPP75, OPP125 and OPPTURBOPLUS and reduce voltages by 3%

further reduction of voltages for MPU, Core and IVA by another 3%
(cherry picked from commit c30f640bc034d51d7548929c397bce9293641a10)
opp4xxx_data: increased by 1.5% to 93.5% of stock voltage values

Increase a bit to improve stability.
(cherry picked from commit 9899ff72115afb26b8d9d0000005fce95de6ef43)
opp4xxx: tweaked GPU overclocking

lowered GPU voltage for mainline kernels
increased GPU speed for ultimate kernels
(cherry picked from commit 62f31762cd20d1a0c5c14fe5c51512b5685f4e94)

Conflicts:

	arch/arm/mach-omap2/opp4xxx_data.c
opp44xx: Update GPU Frequency and voltage value for mainline and ultimate
(cherry picked from commit c38c707837e19e3f43cc6cdf63b3b270af8c18f2)
OPP4xxx_data: Remove over aggressive GPU overclock

this should resolve the instability issues.
(cherry picked from commit 2d745f99bfff48f91279428b8108b68f2cb08ec1)
opp4xxx_data: under volt MPU to 90% of stock

decoupled MPU UV % from IVA and Core
(cherry picked from commit 102c3caf460d2018bc30d89909eb28332756c364)
opp4xxx_data: raise core voltages at 95.0% of stock

since core voltages are used through out the system, raise it higher to
improve stability

mpu is still at 90.0% of stock used by ONLY by CPUs
iva is still at 93.5% of stock used by Audio/Video DSP only
(cherry picked from commit 0dab4acf82a5e32acca901c8863df40b94a99b1a)
opp4xxx: lowered core voltage values and activated forward-body bias

to increase stability for new lowered voltage values.
(cherry picked from commit 0d8d6ddf41a8f2b1da8b61654d7eae80ecf4e9f4)
Overclocking: allow for higher than 1.35GHz Overclocking by enable DCC

add 1.42 and 1.48GHz steps
add NitroSB and NitroSBPlus voltage slots
enable DCC for higher than 1.35GHz clock generation
(cherry picked from commit 28be1d59a9b002545b2b86c4c1c09462a46a02a8)
ARM: OMAP4460: Fixed missing dependency map of OPP for iva

ARM: OMAP4460: Fixed missing dependency map of OPP for iva

Added missing dependency map of OPP-Nitro and OPP-SpeedBin for iva.
Without this line setting IVA into high OPP fail with errors:

rpres iva.0: _dep_scan_table: 1375000 volt map missing in vdd_core
rpres iva.0: omap_device_scale: Error in scan domains for vdd_iva

Change-Id: I73df4897e886a2d4c9fa22abcbc8a6f34c2a8503
Signed-off-by: Vitaly Chernooky <vitaly.chernooky@ti.com>
(cherry picked from commit 92f8bdc7ea9eef7adc7ba7828be1b1e78bf270ec)
OMAP4: PM: OPP/Clock: Add virtual clocks for high IVA OPPs support

To get correct frequencies for IVA OPP higher than OPP100
IVA DPLL should be reconfigured.
Tesla is also supplied from the same IVA DPLL, so frequency on DSP
should be reconfigured together with IVAHD frequency.

This is achieved by adding virtual clocks for IVA and DSP.
Main logic is implemented in IVA virtual clock which sets
frequency for both IVAHD and DSP.
DSP virtual clock is just a dummy clock and it do nothing.

Necessary DSP OPP is set via IVA virtual clock by using DVFS framework feature:
if device on which OPP is set is not the primary device in voltage domain,
then constraint to the same OPP is set for primary device.
In case of DSP the primary device is IVAHD.

If switching to the lower OPP will cause IVA DPLL scaling up,
then frequency of IVA and DSP should be scaled down before DPLL.

Change-Id: I1b229f1d52f0f8bfa4f65f08221df1e1ba6194bc
[jagadeeshwar.reddy@ti.com: original patch author for 4430]
Signed-off-by: Jagadeeshwar Reddy <jagadeeshwar.reddy@ti.com>
[taras@ti.com: modified and extended for all OMAP44xx]
Signed-off-by: Taras Kondratiuk <taras@ti.com>
modified for tuna by faux123
(cherry picked from commit 8e7f0ce3f9c604037889b2162f1316b5a37d8ec4)
OMAP4: OPP/voltage: Add voltage for IVA OPP NitroSB

On OMAP4460/70 IVA OPP Nitro and OPP NitroSB voltages are the same,
but they should have different nTargets for SmartReflex.
Wrong nTargets lead to lower voltage and possible instability at OPPSB.
(cherry picked from commit ac33d1f6cc921d484301e4e1dcc298f1ac0744ad)

Conflicts:

	arch/arm/mach-omap2/opp4xxx_data.c
OMAP4: OPP: make omap4_mpu_opp_enable generic

Make omap4_mpu_opp_enable generic using the omap_hwmod_name_get_dev api
so that we can reuse it for other devices as well. As part of this,
rename it to omap4_opp_enable.
(cherry picked from commit cc3a3645ab88e12aff5909f740cc57b5984fcbb0)