Enable ARCH_POWER to use arm_cpu_topology power management features.
ARM: tegra: emc: Reduce DDR3 min rate to 25.5MHz. - from NVIDIA
Revert "ARM: tegra: power: Trim Tegra3 hotplug timings"

This reverts commit 22f5ad8d6101d98c09d1256f43955cca84e61d5e.
ARM: tegra3: Fine tune hotplug driver. - from NVIDIA
ARM: tegra: power: Don't enter LP2 if not in NOHZ mode

Prevent Tegra3 secondary CPU entry to LP2 state when scheduler tick
is not switched to NOHZ mode, yet.

Bug 945658

Change-Id: I31e43f7890f09af269beda768e848b3e0fb4b313
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/87474
Reviewed-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Tested-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit 1c348149ae3bb07c52a53f8600813d6c85277dfc)

ARM: tegra: power: Fix Tegra3 LP2 stats

Fixed Tegra3 LP2 stats to account for total completed and interrupted
LP2 time (interrupted LP2 time was missed).

(cherry picked from commit 4207244f6fc25544315fe5aaf067ea7684731d9d)

Change-Id: I3b87819d56e3a700f7e0858fa124b0fdfabe8295
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/73902
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit ee2dd3a57c91ba63728e78b8d0f9b735fa0b9df1)

ARM: tegra: power: Don't over-sleep LP2 on secondary CPUs

Adjust Tegra3 secondary CPU LP2 time for exit latency to avoid
scheduler event over-sleep.

Change-Id: I33aa7566eb8763099ae2fc2dc7b3f42a752352f4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/78635
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit 433a3e356a0281efb1caf9b78bb1576008a58ed2)

ARM: tegra: power: Separate lp2 latency for secondary CPUs

Do not use common lp2 exit latency for Tegra3 secondary CPUs in
G mode. Separately measure and adjust latency on each slave CPU;
use per-cpu latency to determine target residency threshold for
entering lp2 on each CPU.

Change-Id: I4470d1b4814d8f12129e21105dd952a903084f1e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/78375
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
(cherry picked from commit cfba9ceaae3be7fca988b2b460b655144e66c2b2)

ARM: tegra: power: Separate lp2 latency for G/LP CPU modes

Do not use common lp2 exit latency for Tegra3 CPU G and CPU LP modes.
Separately measure and adjust latency in each mode; restart calculation
after mode switch from the last measured latency in the target mode.

Change-Id: I54803c6abf4107a578aa1fed8feaa4a419a9c07f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/78344
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
(cherry picked from commit 45986459144b6af477fec937b627f55bf517b92e)

ARM: tegra: power: Re-factor Tegra3 secondary CPU LP2 entry

When Tegra3 secondary CPU is entering LP2, read TWD timer state
into context structure, rather than separate local variables.

Change-Id: I237eafc50a11d535b94f334631d039ba9c4bf44b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/77957
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
(cherry picked from commit eccb57527e305ec8d1ac4e472d891a2e0d5baf34)

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Change-Id: I099efb047698ce4b4b6d53341be151dee2419a4d
Reviewed-on: http://git-master/r/97868
Reviewed-by: Allen Martin <amartin@nvidia.com>
tegra:cpuidle:remove flow-controller programming

bug 937980

Remove some legacy flow-controller programming from LP3 entry and exit
paths. Also remove data synchronization barrier instruction after wfi
to improve scaling across cores.

Change-Id: I7e9e8e7106e77d2abf93a716426930c224d877ed
Signed-off-by: satya popuri <spopuri@nvidia.com>
Reviewed-on: http://git-master/r/86451
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit f88ee65418126365fc10af3d3771bba5d2e41d57)

ARM: tegra: power: Report LP3 state if LP2 is not allowed

Properly report LP3 state to idle governor when LP2 entry is not
allowed and LP2 request is redirected to LP3.

Change-Id: If4bdf6b635d7b40a8958dc5357903c4ea563d112
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/77956
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit 4cf479b35d5314b81becdfbf4cc8d4b1224dcb94)

Change-Id: I85ba0e786f22b914ed03df085b521a2579ff576d
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-on: http://git-master/r/98176
Reviewed-by: Allen Martin <amartin@nvidia.com>
ARM: tegra: dvfs: Expand Tegra3 cpu dvfs tables

Expand Tegra3 cpu dvfs tables to add characterization results
for 800mV VDD_CPU.

Bug 817679
Bug 841336

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/77936
(cherry picked from commit f5b488019895c83e05ded8a8912cf3eb4eea5686)

Change-Id: Id7e5a46c96c67ca80f552b742cf3cf341bb8e1f0
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/80000
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Conflicts:

	arch/arm/mach-tegra/tegra3_dvfs.c
ARM: tegra: dvfs: Update Tegra3 CPU DVFS tables

Bug 817679
Bug 841336

Change-Id: I9a9d9e7a03b64774b1d2ebd8533be85582827515
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/71755
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Conflicts:

	arch/arm/mach-tegra/tegra3_clocks.c
	arch/arm/mach-tegra/tegra3_dvfs.c
ARM: tegra: dvfs: Update Tegra3 vdd_core floor

To properly account for voltage steps with 12.5mV resolution, moved
up by 25mV all thresholds in vdd_core floor calculation function, and
replaced "less than or equal" comparison with "less than".

Change-Id: I869ecabf4e25a268fbe279e54026d4fd1bf25db6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/73903
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-on: http://git-master/r/74558
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

Conflicts:

	arch/arm/mach-tegra/tegra3_dvfs.c
ARM: tegra: dvfs: Add Tegra3 x7 CPU dvfs entries

Bug 841336
Reviewed-on: http://git-master/r/76912

Change-Id: I2806c8e4f08af49edf57f00a43438b1503d6aedb
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78706
Reviewed-by: Automatic_Commit_Validation_User

Conflicts:

	arch/arm/mach-tegra/tegra3_dvfs.c
ARM: tegra: dvfs: Add Tegra3 x7 core dvfs

- Added Tegra3 x7 core dvfs entries
- Increased EMC, graphics, and UART clocks maximum limits
- Updated PLLC configuration table

Bug 841336
Reviewed-on: http://git-master/r/76942

Change-Id: Ifa235e60d66d959ad589574c5ebde90eb0b65385
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78707
Reviewed-by: Automatic_Commit_Validation_User

Conflicts:

	arch/arm/mach-tegra/tegra3_clocks.c
ARM: tegra: dvfs: Expand Tegra3 cpu dvfs tables

Expand Tegra3 cpu dvfs tables to add characterization results
for 800mV VDD_CPU.

Bug 817679
Bug 841336

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/77936
(cherry picked from commit f5b488019895c83e05ded8a8912cf3eb4eea5686)

Change-Id: Id7e5a46c96c67ca80f552b742cf3cf341bb8e1f0
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/80000
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Conflicts:

	arch/arm/mach-tegra/tegra3_dvfs.c
ARM: tegra: dvfs: Fix Tegra3 cbus limit at 1.35V

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit e031d09197f7b4214ad035b1acf7d6c39049021e)

Change-Id: Ie3dc75aa2997c52b7e5aa80c35165c8c4284b8ec
Reviewed-on: http://git-master/r/83288
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
ARM: tegra: dvfs: Update T30L and T30SL Vcore min values.

Update T30L and T30SL values Vcore min voltage is now
1.2V when Vcpu >= 1.1V. Old setting was 1.3V.

Bug 841336
Signed-off-by: Gaurav Sarode <gsarode@nvidia.com>

Change-Id: I35202189618cffd4ead1fae3db462c3e970a7ed8
Reviewed-on: http://git-master/r/86912
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Gaurav Sarode <gsarode@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
ARM: tegra3: dvfs: Changed max values of clocks

Changed clock frequency of some clocks as per
Automotive POR.

Bug 882186

Signed-off-by: Mohit Kataria <mkataria@nvidia.com>
Reviewed-on: http://git-master/r/75210
(cherry picked from commit 9cc17e9cddfedc6fe977f103c5e21ae3f82c3496)

Change-Id: Ibb0e79e75c2fca7d9f09d373c163ef08cc636819
Reviewed-on: http://git-master/r/90490
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Mohit Kataria <mkataria@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>

Conflicts:

	arch/arm/mach-tegra/tegra3_clocks.c
Revert "ARM: tegra: dvfs: Set Tegra3 VDD_CORE min to 1.1V"

This reverts commit db462754240e2ee6cf85e1253b1475a330ea0dfe -
temporary work-around for bug 870300 is no longer needed.

Change-Id: I3b76c01eef89cd80134210926e6623f0494626dd
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/89874
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
ARM: tegra: dvfs: correct LCD frequency for 1V

Bug 841336

Reviewed-on: http://git-master/r/82996
(cherry picked from commit 5850c8f4968fd7acbb22e377a56a476e37ac5117)

Change-Id: I61d5c1576a6f5caf82b3efec2123c47eb64889b2
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/88865
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: clock: Add LPDDR2 temperature controls

Added interfaces for
- reading scaled  LPDDR2 temperature from MR4 register
- controlling refresh rate according LPDDR2 specification

For now, these interfaces are only used by debufs nodes:

/sys/kernel/debug/tegra_emc/dram_temperature (read only)

/sys/kernel/debug/tegra_emc/over_temp_state (read/write,
0 - set regular low temperature refresh rate,
1 - speed up refresh for high temperature)

Bug 939626

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 373ff7e49235f6e222b42e324b6a2dc9eac633e6)

Change-Id: I9cfaaeeab16d5b49acb91824fecc6b0ee8f3cdbb
Reviewed-on: http://git-master/r/89349
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Conflicts:

	arch/arm/mach-tegra/tegra3_emc.c
mmc: host: sdhci: Allow use of controller's native max blocksize

Currently, any controller supporting a blocksize of 4K or higher
is bumped back down to 512 bytes. This change allows using the
controller's native blocksize on a per-hardware basis.
arm: tegra: pm: Update CPU complex resume

Completely removed PLLP restoration from CPU complex resume on
Tegra2 platforms (too late: PLLP is restored from AVP warm boot
code)

Bug 952200
Bug 931285

Change-Id: I51ca17a943bcbd5753764b4e3c20877519943e27
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/92523
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
(cherry picked from commit 066dc172010f1a5ea5a375e1cbdcf162ab206d63)

ARM: tegra: clock: Update secondary pll dividers resume

During resume from LP0 on Tegra3 always enable pll secondary dividers
before clocks restoration (to make sure clock sources are enabled).
Restore actual secondary dividers settings after clocks are restored.

Remove pllp secondary dividers restoration from cpu complex restore,
and add them to common clock restoration procedure. These dividers
are not affected by CPU complex suspend, only by LP0 core suspend.

Change-Id: I8a09006fad935f8e1cb74c14a87f6246060ba182
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/79938
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit 1f631436717c0602ef30770f7976615150114afe)

ARM: tegra: power: Update CPU complex resume

- Completely removed PLLP restoration from CPU complex resume on
Tegra3 platforms (too late: if necessary PLLP is restored by LPx
exit code on Tegra3, and attempt to restore it again does not do
any good).

- Restored PLLX only if it is not already used as CPU source
(it is dangerous to restore PLL in use).

- Restore burst policy on exit from LPx states, but preserve it
after cluster switch, as it maybe different for LP and G clusters.

Change-Id: Ia5ff24d22a2135494bc3442f92bebcc1953c7f08
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/72535
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
(cherry picked from commit d278b71cf09fbbdbc9db81427eff0f9053a97b24)

ARM: tegra: Do not flush complete L2 at LP2 entry

There is no need to flush the complete L2 upon LP2
entry. It is sufficient to clean the page table
entries needed by LP2 code sequence that has L2 off
and MMU on.

Bug 931316

Change-Id: I40ce0444e6980147bb499be5cd0abd9907040288
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/85483
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
(cherry picked from commit f474cf90920679789b9612724f1e2cd6dfdbfbbd)
Conflict:
	arch/arm/mach-tegra/pm.c

ARM: tegra: power: Fix warnings when PM_SLEEP is not selected

Change-Id: I88939c92aa1c28f5177010ba2afd524c3a4b713d
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/76686
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
(cherry picked from commit 9697b8a6b6445e1aebf8da5ccf343e2fc2b65cdc)

ARM: tegra: power: Fix Tegra2 power timer rate

Commit 0142197cf7b1828fa7935c9d8715f37313864db1 implemented LP0
state entry with fast CPU and system bus clocks only for Tegra3,
but changed power timers rate calculation in the common Tegra2
and Tegra3 path. Fixing it now.

Change-Id: Ib8d5743edda680e9e2658449fe43811549d0603f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/84716
Reviewed-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit 9e66d6adf6ab1fe06eee63baf0f1f684715d1ae2)

ARM: tegra: power: Don't lower clocks on LP0 entry

Do not change (lower) CPU and system clocks, and do not disable PLLs
on entry to LP0, since all clocks and PLLs are stopped in h/w, anyway.

Change-Id: I1c9f2f5c0c4259b6c4b0cbed1fcd33ffd7e9231c
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/83319
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
(cherry picked from commit 0142197cf7b1828fa7935c9d8715f37313864db1)

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Change-Id: Iabbf0785ba7d260c0244fe8b687966b9a16e8d96
Reviewed-on: http://git-master/r/99040
Reviewed-by: Allen Martin <amartin@nvidia.com>