Remove 'SHIPPED' library ashlidi3.S added with the xz commit
ignore ashldi3.S
lib: Introduce some memory copy macros and functions

The kernel's memcpy and memmove is very inefficient. But the glibc version is
quite fast, in some cases it is 10 times faster than the kernel version. So I
introduce some memory copy macros and functions of the glibc to improve the
kernel version's performance.

The strategy of the memory functions is:
1. Copy bytes until the destination pointer is aligned.
2. Copy words in unrolled loops. If the source and destination are not aligned
   in the same way, use word memory operations, but shift and merge two read
   words before writing.
3. Copy the few remaining bytes.

Signed-off-by: Miao Xie <miaox@...fujitsu.com>

Conflicts:

	lib/Makefile
lib: Improve the performance of memcpy and memmove of the general version

The performance of memcpy and memmove of the general version is
very inefficient, this patch improves them.
lib/sha1: use the git implementation of SHA-1

For ChromiumOS, we use SHA-1 to verify the integrity of the root
filesystem.  The speed of the kernel sha-1 implementation has a major
impact on our boot performance.

To improve boot performance, we investigated using the heavily optimized
sha-1 implementation used in git.  With the git sha-1 implementation, we
see a 11.7% improvement in boot time.

10 reboots, remove slowest/fastest.

Before:

  Mean: 6.58 seconds Stdev: 0.14

After (with git sha-1, this patch):

  Mean: 5.89 seconds Stdev: 0.07

The other cool thing about the git SHA-1 implementation is that it only
needs 64 bytes of stack for the workspace while the original kernel
implementation needed 320 bytes.

Signed-off-by: Mandeep Singh Baines <msb@chromium.org>
Cc: Ramsay Jones <ramsay@ramsay1.demon.co.uk>
Cc: Nicolas Pitre <nico@cam.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: linux-crypto@vger.kernel.org
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
arm: remove "optimized" SHA1 routines

Since commit 1eb19a12bd22 ("lib/sha1: use the git implementation of
SHA-1"), the ARM SHA1 routines no longer work.  The reason? They
depended on the larger 320-byte workspace, and now the sha1 workspace is
just 16 words (64 bytes).  So the assembly version would overwrite the
stack randomly.

The optimized asm version is also probably slower than the new improved
C version, so there's no reason to keep it around.  At least that was
the case in git, where what appears to be the same assembly language
version was removed two years ago because the optimized C BLK_SHA1 code
was faster.

Reported-and-tested-by: Joachim Eastwood <manabian@gmail.com>
Cc: Andreas Schwab <schwab@linux-m68k.org>
Cc: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
arm: remove stale export of 'sha_transform'

The generic library code already exports the generic function, this was
left-over from the ARM-specific version that just got removed.

Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
cpufreq: interactive: fix possible Division by zero.

The following dump was seen sometimes while resuming,
the only division by zero on this function can happen after
delta_time is reassigned, since at the start of the
function, there is jump that protects against values
less than 1000.

After that, If delta_time and delta_idle == 0,
we will hit a div 0

Division by zero in kernel.
Backtrace:
[<c0057184>] (dump_backtrace+0x0/0x110) from [<c05d5ecc>] (dump_stack+0x18/0x1c)
r6:010f3000 r5:c113dfb0 r4:c004afb0 r3:c6ff0000
[<c05d5eb4>] (dump_stack+0x0/0x1c) from [<c00572cc>] (__div0+0x1c/0x20)
[<c00572b0>] (__div0+0x0/0x20) from [<c02195d4>] (Ldiv0+0x8/0x10)
[<c03dfd64>] (cpufreq_interactive_timer+0x0/0x2c0) from [<c00a7efc>] (run_timer_softirq+0x154/0x260)
[<c00a7da8>] (run_timer_softirq+0x0/0x260) from [<c00a0c8c>] (__do_softirq+0xc8/0x194)
[<c00a0bc4>] (__do_softirq+0x0/0x194) from [<c00a1008>] (irq_exit+0xb4/0xb8)
[<c00a0f54>] (irq_exit+0x0/0xb8) from [<c00584b4>] (ipi_timer+0x44/0x48)
r4:c004a040 r3:00000001
[<c0058470>] (ipi_timer+0x0/0x48) from [<c004c3e4>] (do_local_timer+0x68/0x84)
r5:c004ae2c r4:c07991e8
[<c004c37c>] (do_local_timer+0x0/0x84) from [<c0052948>] (__irq_svc+0x48/0xe0)
cpufreq interactive: support shared CPU scaling

Change-Id: Id5267f04067bf023f6b140b4de2e88ef7287e941
Signed-off-by: Todd Poynor <toddpoynor@google.com>
cpufreq: interactive: remove debug trace code

Remove debug trace code in preparation of upstreaming

Change-Id: I0905885e75031f5e9d7cb06878fb68c1fd06d4fe
Signed-off-by: Allen Martin <amartin@nvidia.com>
cpufreq: interactive: Add error checking on sysfs interfaces

This adds better error checking on tunable parameters on sysfs
interfaces.  Also fixes return value from these functions, previously
on success they would return 0 which would cause a infinite loop.

Change-Id: Ic05038492166f8673d007202092471f98a2f0dfa
Signed-off-by: Allen Martin <amartin@nvidia.com>
cpufreq: interactive: add sysfs control for timer rate

Add a new sysfs control that tunes the rate of the timer used to
increase cpu frequency

Change-Id: I1aa13ae54bb43aff5b3688984d2955f56aae1658
Signed-off-by: Allen Martin <amartin@nvidia.com>
cpufreq: Add more verbose description of interactive governor

Update the Kconfig help paragraph to give more detail about
interactive governor.

Change-Id: I607b817b370accac3a685001649a15e2f7894f59
Signed-off-by: Allen Martin <amartin@nvidia.com>
cpufreq: interactive: fix checkpatch warnings on long lines

Fix up checkpatch warning introduced by long lines in timer_rate
patch.

Change-Id: I22b105dafb1b49390799bb7577464da03f0f8afb
Signed-off-by: Allen Martin <amartin@nvidia.com>
cpufreq: interactive governor: default timer 10ms, maxspeed load 95%

Modify default timer from 30ms to 10ms, sampling 2 jiffies after
idle exit on ARM as in Honeycomb.

Modify default go_maxspeed_load from 85% loaded to 95% loaded, for
use in phones where power savings is more important (tablets may be
best served overriding this).

Change-Id: I3361a6279979bfae1df5262666a2e30ea7a44328
Signed-off-by: Todd Poynor <toddpoynor@google.com>
power: cpufreq interactive governor: use default sample time 20ms

Lower the default time at which a higher speed is allowed to run
before lowering based on lower CPU load from 80ms to 20ms.  Most
Android devices should trade power for performance here,
although tablets and non-battery-powered devices may want to
override this default.

Change-Id: I1a4f7faeca12793c51d5b92db30a63cca8d4f1be
Signed-off-by: Todd Poynor <toddpoynor@google.com>

Conflicts:

	drivers/cpufreq/cpufreq_interactive.c
cpufreq: interactive governor: apply intermediate load on current speed

Calculate intermediate speed by applyng CPU load to current speed, not
max speed.

Change-Id: Idecf598b9a203b07c989c5d9e9c6efc67a1afc2e
Signed-off-by: Todd Poynor <toddpoynor@google.com>
cpufreq: interactive governor: scale to max only if at min speed

Change-Id: Ieffb2aa56b5290036285c948718be7be0d3af9e8
Signed-off-by: Todd Poynor <toddpoynor@google.com>
cpufreq: interactive governor: go to intermediate hi speed before max

* Add attribute hispeed_freq, which defaults to max.

* Rename go_maxspeed_load to go_hispeed_load.

* If hit go_hispeed_load and at min speed, go to hispeed_freq;
  if hit go_hispeed_load and already above min speed go to max
  speed.

Change-Id: I1050dec5f013fc1177387352ba787a7e1c68703e
Signed-off-by: Todd Poynor <toddpoynor@google.com>
cpufreq: interactive governor: default 20ms timer

Change-Id: Ie9952f07b38667f2932474090044195c57976faa
Signed-off-by: Todd Poynor <toddpoynor@google.com>

Conflicts:

	drivers/cpufreq/cpufreq_interactive.c