OMAP3: PM: Make secure RAM save size configurable

OMAP3 users of HS/EMU devices at times choose to use their
own PPA which could be configured to use different sized storage
area based on their security needs. Convert the hardcoded size
define to a more configurable form to map to these users. we introduce
the structure omap3_secure_copy_data to describe PPA specific behavior
we will further populate in follow on patches. secure_copy_data_set
is introduced to allow for board files to populate custom parameters
as desired.

This is from p-android-omap-2.6.32 f71d48fbe77e20ef8964ad81930fb42cc000e4cc

Change-Id: I359a72b5f9412106e31a839a3a708228e066dca9
Signed-off-by: Steve Schefter <sschefter@ti.com>
Signed-off-by: Jack Miller <jack.miller@ti.com>
Signed-off-by: jack.miller <jack.miller@ti.com>
OMAP3: PM: Allocate secure RAM context memory from low-mem

Currently memory is allocated from kernel heap, which is located at high-mem.
Low-mem allocation is needed due to OMAP3630 SDRC CKE1 bug, high-mem (i.e.
CS1 area) is not accessible by boot ROM code after wakeup from off-mode.

From p-android-omap-2.6.32 commit 4acbc48de6cbc680a6b2b6fe16b9238f62b562b4

Change-Id: I88223ab6c34ea97245831a467eeba4604713a820
Signed-off-by: Steve Schefter <sschefter@ti.com>
Signed-off-by: jack.miller <jack.miller@ti.com>
OMAP3:PM:Save secure RAM over OFF in EMU

Save secure RAM context over OFF for EMU/HS devices.

This resolves the errata which requires EMU/HS devices to
save context and restore each time entering and resuming
from Chip OFF mode.

Platform freezing bug was due to save/restore secure services
while transitioning from public-->secure side.

Instead of saving context only once during Boot sequence, this
patch allows to save each time OFF transition happens.

From p-android-omap-2.6.32 commit 03bbf001d95e5cd24b90000494bc63a070348c37

Change-Id: Ifdd8aca8982fcc743daa8326d2e6f8af9c42d6a0
Signed-off-by: Steve Schefter <sschefter@ti.com>
Signed-off-by: jack.miller <jack.miller@ti.com>
PM: Deny MPU idle while saving secure RAM

Deny MPU idle before save secure ram and allow it after save secure RAM.
We want to deny MPU going to low power state because, there is a short
time window where a wakeup event would happen around the time the MPU
is going to idle. Since the first thing ROM code does after WFI is to
read INTCPS register, we could reach a situation where the INTCPS is
in idle, but the read is sent to it. That would produce a data abord
during the save of secure ram, which will hang the system. we need
to prevent clock transitions as well during this timeframe.

[nm@ti.com: rebased to 2.6.37-rc2, used omap2_clkdm_deny_idle for
clock prevention]

Patch taken from L-O tree Posted by Nishanth Menon

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com>
Signed-off-by: Deepak K <deepak.k@ti.com>

Change-Id: I05f6623f22b5437587c1485b891a7e5270d33939
Signed-off-by: Steve Schefter <sschefter@ti.com>
Signed-off-by: jack.miller <jack.miller@ti.com>
OMAP3: PM: Fix secure ram save size

Use TI recommended save_secure_ram size for OMAP3 using TI official
OMAP3 PPA.

As per TRM HS/EMU requires 60K sram size.

Note: custom platforms may have different save sizes.

Signed-off-by: Nishanth Menon <nm@ti.com>
[Android-porting]
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>

Change-Id: I5e27718033869eddbece66a4481dca9294b589c4
Signed-off-by: jack.miller <jack.miller@ti.com>
Signed-off-by: Steve Schefter <sschefter@ti.com>
OMAP3: PM: Allow core clocks to turn off

Although the core domain was turning off, the core clocks were not turning
off as indicated by T2 - CLKREQ on the debug board.

Change-Id: Ia9005bfb37c3931df023a1ad11e414e652ec2307
Signed-off-by: Steve Schefter <sschefter@ti.com>
OMAP3: PM: Fix warning "MPU wakeup but no wakeup sources"

This fix was originally from
Madhusudhan Gowda <ext-madhusudhan.1.gowda@nokia.com>.  The following is
the original commit message.

  A corner case where prcm_interrupt handler is handling the WKST_WKUP
  and before acknowledging the wakeup sources if an IO Pad wakeup ST_IO
  is indicated then hits the below warning since the wakeup sources are
  already cleared.
	WARN(c == 0, "prcm: WARNING: PRCM indicated "
		"MPU wakeup but no wakeup sources "
		"are marked\n");

  Since the above warning condition is only valid if the prcm_interrupt
  handler is called but no wakeup sources are marked in first iteration.

  The patch fixes this corner case.

  Updated after Paul Walmsley's "only handle selected PRCM interrupts" patch.

  Signed-off-by: Madhusudhan Gowda <ext-madhusudhan.1.gowda@nokia.com>

Additional fixes from the following thread were applied.
https://patchwork.kernel.org/patch/339131/

Change-Id: Ib44169a8e45fd330ed4d6b6aec5484b376912fad
Signed-off-by: Hong H. Pham <hong.pham@ti.com>
OMAP3: PM: Fixed glitches in GPIO outputs during off-mode transitions

Output GPIOs managed by the PER power domain will lose their context
during wakeup from off-mode, causing a short glitch in the output level
until the GPIO context can be restored.  Pad configuration must be used
to set output pins to input with pull-up/pull-down depending on level.
PER must use hardware supported transition to idle only, and it needs
a wakeup dependency on WKUP and CORE.  When restoring the GPIO context,
the DATAOUT register must be restored before the OE register.

See OMAP3 errata i468 for more details.

Change-Id: I4383273403880c55199223b40608545c0576f3d7
Signed-off-by: Carl Benson <cbenson@windriver.com>
Signed-off-by: Steve Schefter <sschefter@ti.com>
Signed-off-by: Hong H. Pham <hong.pham@ti.com>
OMAP3: PM: use add/del sleepdep for DSS powerdomain on omap_sram_idle()

DSS is entered to OFF when the core OFF or lcd off state.
I've checked a lot of things. But, DSS is entered to OFF state
only if set sleepdep for mpu.

Change-Id: I286e9dbc197e9d32eedb3d590650ab3652626289
Signed-off-by: wonjong.lee <wonjong.lee@ti.com>
OMAP3: PM: Support for turning off VDD1/VDD2 via SYS_OFFMODE

Add support for indicating to the PMIC via the SYS_OFFMODE pin that
it should turn off VDD1 and VDD2.  Without this, the PMIC is told
about suspend via I2C.  However, I2C commands can only drop VDD1
and VDD2 to 0.6V, not 0V.  The SYS_OFFMODE method is enabled via
voltage_off_while_idle in debugfs (written by the init script).
This patch also fixes a bug in the routine which writes the
sleep script to the PMIC so that SYS_OFFMODE has the expected
result.

Change-Id: Iffced7b2614df2dda93f49a5da4e5f456030deb8
Signed-off-by: Steve Schefter <sschefter@ti.com>
USB PM: Fix power off mode when USB cable not attached

The board was not coming to power off mode when USB
cable was detached because the OTG_SYSCONFIG register
setting was toggled between smartstandby and forcestandby
in musb_context_save/restore. This new code does not work
on OMAP3630 revisions earlier than ES1.2 since it will
randomly crash when coming out of power off, so older boards
will still not power off when USB is not attached.

Change-Id: I268552ae3244642710064ef397e06512a0345f28
Signed-off-by: Carl Benson <cbenson@windriver.com>
Signed-off-by: Steve Schefter <sschefter@windriver.com>
omap3: pm: ensure IO wakeups are properly disabled

This is a port of below patch submitted by Kevin on Linux Mainline.
---------------------------------------------------------
    During idle, if the PER powerdomain transitions into a lower state
    and CORE does not, the IO pad wakeups are not being disabled in
    the idle path after they are enabled. This can happen with the
    lower C-states when using CPUidle for example.

    This patch ensures that the check for disabling IO wakeups also checks
    for PER transitions, matching the check done to enable IO wakeups.

    Found when debugging PM/CPUidle related problems reported by Ameya
    Palande <ameya.palande@nokia.com>.  Problems were triggered
    particularily on boards with UART2 consoles (n900, Overo) since UART2
    is in the PER powerdomain.

    Tested on l-o master (omap3_defonfig + CONFIG_CPU_IDLE=y) as well
    as with current PM branch.  Boards tested: n900, Overo, omap3evm.

    Cc: Paul Walmsley <paul@pwsan.com>
    Cc: Ameya Palande <ameya.palande@nokia.com>
    Tested-by: Jarkko Nikula <jhnikula@gmail.com>
    Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
    [tony@atomide.com: updated description to clarify the transistion]
    Signed-off-by: Tony Lindgren <tony@atomide.com>
-------------------------------------------------------------

Original-Author: Kevin Hilman
Change-Id: I6248a1bd0a83f77eeab6453a637ace1a426978e2
Signed-off-by: Mohan V <mohanv@ti.com>
OMAP 3630 ES1.0 and ES1.1 errata i583 workaround

Change-Id: Id16256045aa3c3793fcef3680f9c3d24c5310a8d
Signed-off-by: Michael Barabanov <michael.barabanov@ti.com>
omap3: pm: correct enable/disable of daisy io chain

Currently the enabling and disabling of IO Daisy chain is not
according to the TRM. The below steps are followed to enable/
disable the IO chain according to the OMAP36xx_ES1.x Public
TRM "Sec 3.5.7.2.2 I/O Wake-Up Mechanism".

Steps to enable IO chain:
[a] Set PM_WKEN_WKUP.EN_IO bit
[b] Set the PM_WKEN_WKUP.EN_IO_CHAIN bit
[c] Poll for PM_WKST_WKUP.ST_IO_CHAIN. When set to 1, clear it.

Steps to disable IO chain:
[a] Clear PM_WKEN_WKUP.EN_IO_CHAIN bit
[b] Clear PM_WKEN_WKUP.EN_IO bit
[c] Clear PM_WKST_WKUP.ST_IO bit by writing 1 to it.

Steps [c] in both cases can be skipped, as these are handled by
the PRCM interrupt handler later.

Tested-on: ZOOM3 ES1.2 Board

Change-Id: I55eefedd8aca0850b790265f0cc1d6f39aa8eff2
Signed-off-by: Mohan V <mohanv@ti.com>
OMAP3: PM: Errata i582: per domain reset issue: uart

The original patch could be found at the following URL, and was integrated
with some minor changes.
https://patchwork.kernel.org/patch/338081/

The following is the patch's commit message.

  From: Archana Sriram <archana.sriram@ti.com>

  Errata Id:i582

  PER Domain reset issue after Domain-OFF/OSWR Wakeup.

  Issue:
  When Peripheral Power Domain (PER-PD) is woken up from OFF / OSWR
  state while Core Power Domain (CORE-PD) is kept active, write or
  read access to some internal memory (e.g., UART3 FIFO) does not
  work correctly.

  Workaround :
  * Prevent PER from going off when CORE has not gone to off.
  * When both CORE-PD and PER-PD goes into OSWR/OFF, PER-PD should be
  brought to active before CORE-PD.This can be done by configuring a wakeup
  dependency so that CORE-PD and PER-PD will wake up at the same time.

  Acked-by: Tero Kristo <tero.kristo@nokia.com>
  Tested-by: Eduardo Valentin <eduardo.valentin@nokia.com>
  Tested-by: Westerberg Mika <ext-mika.1.westerberg@nokia.com>

  [vishwanath.bs@ti.com: initial code and suggestions]
  Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
  [nm@ti.com: forward ported to 2.6.37-rc2 and suggestions]
  Signed-off-by: Nishanth Menon <nm@ti.com>
  Signed-off-by: Archana Sriram <archana.sriram@ti.com>

Change-Id: I3cec92018fc77f4ccf777b10bf781a9e5e1f8eea
Signed-off-by: Hong H. Pham <hong.pham@ti.com>
OMAP3:PM: fix for IVA2/PER/CORE not transit to target state

Issue is with only RET enabled in enable_off_mode

    the issue seen is something like this below,
    1. Play mp3, pause it.
    2. Allow bridge inactivity timer to kick in --> puts IVA2 to OFF
    3. Now push powerbutton to do a system wide suspend.
    4. After resume, IVA2, CORE, PER shows failure in attaining the target
       state.

    After step 3, PM tries to sleep switch to put the next state to RET
    (As only RET is enabled). And configures wakedep for IVA on MPU. After
    suspend IVA2/PER/CORE fails to achieve target state.

    Also, point to be noted here is, the iva2_clk is never disabled, it's
    only autoidled. The clk usecount is always one.
    This issue was fixed and validated on .29, porting over .32.
    This commit ports the same patch to .35

Change-Id: I42ee55178cadea6ae5c8776e34cb6cf3cfabefd8
Signed-off-by: Girish S G <girishsg@ti.com>
Acked-by: Akash Choudhari <akashc@ti.com>
Acked-by: Omar Ramirez Luna <omar.ramirez@ti.com>
Signed-off-by: Steve Schefter <sschefter@ti.com>
omap3: prcm: remove the PRM save/restore

This is the port of below Paul Walmsley's patch on mainline.

----------------------------------------------------------
The OMAP3 PRM module is in the WKUP powerdomain, which is always
powered when the chip is powered, so it shouldn't be necessary to save
and restore those PRM registers.  Remove the PRM register save/restore
code, which should save several microseconds during off-mode
entry/exit, since PRM register accesses are relatively slow.

While doing so, move the CM register save/restore code into
CM-specific code. The CM module has been distinct from the PRM module
since 2430.

This patch includes some minor changes to pm34xx.c.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <tero.kristo@nokia.com>
Cc: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
Reviewed-by: Kevin Hilman <khilman@deeprootsystems.com>
Tested-by: Kevin Hilman <khilman@deeprootsystems.com>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Rajendra Nayak <rnayak@ti.com>
----------------------------------------------------------

Limitation: OFF mode is not consistent on ES1.1 Boards.

Change-Id: I4add6ff484f4a70024454d92c4fc2b02931661e2
Signed-off-by: Mohan V <mohanv@ti.com>
OMAP3: PM: disable rta

Errata id: i608
RTA (Retention Till Access) feature is not supported and leads to device
stability issues when enabled. This impacts modules with embedded memories
on OMAP3630

Workaround is to disable RTA on boot and coming out of core off.
For disabling rta coming out of off mode, we do this by overriding the
restore pointer for 3630 to allow us restore handler as the first point of
entry before caches are touched and is common for GP and HS devices.
to disable earlier than this could be possible by modifying the ppa for HS
devices.

Ported from 06179768796791c65637607a93acf5fa3c1cbf0b in 2.6.32 by
Girish S G <girishsg@ti.com>

Change-Id: I25f0e094c4a53e35d0d40515ec7fe25ee05fedb7
Signed-off-by: Steve Schefter <sschefter@ti.com>
OMAP3:PM: PRCM DPLL control FSM removes SDRC_IDLEREQ before DPLL3 locks

When internal SWAKEUP event occurs while CORE DPLL is going to bypass,
PRCM may report that DPLL3 is locked whereas it is not.  This is due to
the timing path of an internal signal which is not fitting to one L3
clock cycle.

In that case, PRCM DPLL control FSM deasserts SDRC_IDLEREQ signal before
DPLL3 Lock state is set.

Consequence is that SDRC is released from IDLE with bypass clock (which
is too low) instead of the locked frequency. DLL may/maynot lock base
on Process Voltage Temperature conditions.

WA as per Errata i581:
    Before RET/OFF:
        1) Reduce DPLL3 M2 Frequency to get L3 running at OPP50 Frequency
        2) Keep volt at 1.1375V
        3) Enable DPLL3 Automatic mode.
    After:
        1) Disable DPLL3 Automatic mode
        2) Restore previous DPLL3 M2 Frequency and CORE Voltage values.

Validated with a scope on VDD2.

Change-Id: Id69d9b0d79f8893186aaa505da9103bab35edb47
Signed-off-by: Steve Schefter <sschefter@ti.com>
OMAP3: PM: usbhost not suspending on ES1.1

In patch de23b5d2198352cbc051220a3cc7c1c162f0a08b a workaround was
implemented for ES1.2 devices which allowed the usbhost and core
domains to turn off.  This was not implemented for ES1.1 devices
due to the author finding ES1.1 devices unstable with this change.
However, I find no issue with ES1.1 devices when running with the
same changes.  And without them, the domains don't turn off when
running from NAND.

Change-Id: Iab6f675f0ab590ddb21000d847aad97f2e3dd518
Signed-off-by: Steve Schefter <sschefter@ti.com>