OMAP4: Android Kernel Names and Versions

Reference patch of the kernel naming and
README on the rules of the naming format
adn when the name need to change.

Change-Id: Ifac1ed946750666b9994f13d6a0d78d002bb01e0
Signed-off-by: Atanas (Tony) Zlatinski <zlatinski@gmail.com>
OMAPDSS: DSSCOMP: Remove PVR_SGX dependency.

In order to disable the in-kernel version of the DDK
and be able to use it as a module we need to remove
this dependency.
No harm to DSSCOMP, it will just wait until a DDK
is installed to execute.

Change-Id: Ie1436a45fb20044d0121eb196c6155b50baa7915
Signed-off-by: Rogelio Garcia <rgarcia@ti.com>
gpu: ion: export needed functions for PVR SGX

Make ion symbols visible to kernel modules. The SGX DDK
in modular form requires these symbols to be exported.

The reason for the code movement of ion structs is due to
EXPORT_SYMBOL’s requirement that the storage size of all
function parameters is known. This is so that the kernel can
sanity-check the size of data structures at module load time.

Change-Id: I2b9efe285557268da3baf258af09b56917add920
Signed-off-by: Rogelio Garcia <rgarcia@ti.com>
omap: Adding opp functions to gpu platform data.

This is required for providing opp framework access to SGX kernel module.

Change-Id: Ie968a6c51ac636b70909257be4c51430c4cc3d48
Signed-off-by: Rogelio Garcia <rgarcia@ti.com>
ARM: OMAP4460: Fixed missing dependency map of OPP for iva

Added missing dependency map of OPP-Nitro and OPP-SpeedBin for iva.
Without this line setting IVA into high OPP fail with errors:

rpres iva.0: _dep_scan_table: 1375000 volt map missing in vdd_core
rpres iva.0: omap_device_scale: Error in scan domains for vdd_iva

Change-Id: I73df4897e886a2d4c9fa22abcbc8a6f34c2a8503
Signed-off-by: Vitaly Chernooky <vitaly.chernooky@ti.com>
OMAP4: ID: Remove code duplication during features check

Standard devices is a subset of Performance device.
So Standard features code can be reused for Performance devices.
This removes code duplication.

Also this patch adds 1.3Ghz flag back.
It was removed by mistake during a merge from p-android-omap-3.0 branch.

Change-Id: Ia993fe9e4d90d0557de54ccd1fd5fcb6e16a2782
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4: ID: Add high IVA OPPs identification

Some 4460 and 4470 devices support IVA OPPNT and OPPSB.
Add flags to identify this feature.

Change-Id: I6e78d95ca07435c60aae36562a2d9b66fcd1baa4
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4: PM: OPP/Clock: Add virtual clocks for high IVA OPPs support

To get correct frequencies for IVA OPP higher than OPP100
IVA DPLL should be reconfigured.
Tesla is also supplied from the same IVA DPLL, so frequency on DSP
should be reconfigured together with IVAHD frequency.

This is achieved by adding virtual clocks for IVA and DSP.
Main logic is implemented in IVA virtual clock which sets
frequency for both IVAHD and DSP.
DSP virtual clock is just a dummy clock and it do nothing.

Necessary DSP OPP is set via IVA virtual clock by using DVFS framework feature:
if device on which OPP is set is not the primary device in voltage domain,
then constraint to the same OPP is set for primary device.
In case of DSP the primary device is IVAHD.

If switching to the lower OPP will cause IVA DPLL scaling up,
then frequency of IVA and DSP should be scaled down before DPLL.

Change-Id: I1b229f1d52f0f8bfa4f65f08221df1e1ba6194bc
[jagadeeshwar.reddy@ti.com: original patch author for 4430]
Signed-off-by: Jagadeeshwar Reddy <jagadeeshwar.reddy@ti.com>
[taras@ti.com: modified and extended for all OMAP44xx]
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4: OPP/voltage: Add voltage for IVA OPP NitroSB

On OMAP4460/70 IVA OPP Nitro and OPP NitroSB voltages are the same,
but they should have different nTargets for SmartReflex.
Wrong nTargets lead to lower voltage and possible instability at OPPSB.

Change-Id: I92558908b4e91eb64680e47e01ff82dedf93aad3
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4: OPP: make omap4_mpu_opp_enable generic

Make omap4_mpu_opp_enable generic using the omap_hwmod_name_get_dev api
so that we can reuse it for other devices as well. As part of this,
rename it to omap4_opp_enable.

Change-Id: I87e76b446fb4e57200edd0ae00f5ff9b70021fa5
Signed-off-by: Nishanth Menon <nm@ti.com>
OMAP4: OPP: enable all higher OPPs for VDD_IVA

The standard PMICs used with OMAP44xx are TWL603x.
OMAP hooks its VDD_IVA net to one of TWL's regulators.

   OMAP   |    PMIC / REG    | Max REG current | Max VDD_IVA current
----------+------------------+-----------------+---------------------
 OMAP4430 | TWL6030 / VCORE2 |    1000mA [1]   |   700mA [3]
 OMAP4460 | TWL6030 / VCORE2 |    1000mA [1]   |  1000mA [4]
 OMAP4470 | TWL6032 / SMPS5  |    1100mA [2]   |  1100mA [5]

Max regulator's current, definitely allows us to enable higher OPPs on VDD_IVA.
This enables the possibility of doing better performing DVFS
on IVA intensive usecases.

VDD_IVA has DSP and IVA devices connected.
This allows the OPP Turbo to be enabled for all OMAP44xx devices.
On OMAP4460/70 OPP Nitro can be enabled for Standard silicon while
OPP NitroSB can be enabled for Performance silicon.

Footnotes:
[1] TWL6030 datasheet SWCS045B (June 2011)
[2] TWL6032 datasheet SWCS075C (Nov 2011)
[3] OMAP4470 Data Manual SWPS045B (Oct 2011)
[4] OMAP4460 Data Manual SWPS042J (Nov 2011)
[5] OMAP4430 Data Manual SWPS040P (Oct 2011)

Change-Id: I2a812bb1b65ec5d0c2321d65695d844b6c01792d
[nm@ti.com: original patch author]
Signed-off-by: Nishanth Menon <nm@ti.com>
[taras@ti.com: added OMAP4470 part]
Signed-off-by: Taras Kondratiuk <taras@ti.com>
MFD: twl6040-codec: Add TWL6041 ES2.0 version id

Add definition for TWL6041 ES2.0 version.

Change-Id: I643b06c6f48479bcc76a43131a418b51fbbc6ee6
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
ASoC: twl6040: Fix HS DACs DC offset errata

Current implementation of HSDACs DC offset errata disables DACR when
headset and earpiece outputs are used simultaneously. A simpler approach
is used:

- Headset DAC Left:
  o HSDACR must be enabled before enabling HSDACL, since HSDACL reset is
    done when HSDACR is enabled
  o No additional handling required for power-down

- Headset DAC Right:
  o No special handling required for power-up
  o HSDACR reset is done when HSDACL is enabled, so in case DACL was
    already disabled, re-enabled it momentarily while HSDACR power-down
    occurs.

Change-Id: I20f29602268d701b64c10dfa86cc43f66b8325b0
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
ASoC: twl6040: Use HS DC offset errata for TWL6041 ES2.0

Headset DC offset errata also applies for TWL6041 ES2.0.

Change-Id: Ia1c6f837507d146d137fd62e3e500ad427cad233
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
ASoC: twl6040: Split HF DAC event handler

Use a dedicated event handler for HS DAC widgets whose only task is
wait for the settling time of at least 80us.

Change-Id: I2f13051fdc02466c184cf2ee9ed5653b75644023
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
ASoC: twl6040: Reorder HSDAC/DRV power mode change

HSDAC and HSDRV power mode change cannot be performed when the
corresponding DAC is enabled, which is now explicitly rejected.
This constraint has an important impact on eapiece path, since
it can work only in high-performance mode.

In such case, we need to force the power mode before enabling
the DACs and restore previous mode after DACs have been disabled.
That sequence cannot be achieved if the event is associated with
a switch widget, so using a supply widget instead.

Change-Id: I3bddf3dc6fc038c78f83f1eb6f21f578c80cfee2
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
ASoC: twl6040: Reduce i2c writes during power mode change

Replace direct i2c writes to TWL6040 by calls to snd_soc_update_bits()
which prevents unnecessary i2c writes when reg cache and hardware are
in sync.

Change-Id: I8bb02d83fb419a478707d33498a95efa6e98a45c
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
OMAP: clock: fix race in disable all clocks

clk_disable_unused is invoked when CONFIG_OMAP_RESET_CLOCKS=y.
Since clk_disable_unused is called as lateinitcall, there can
be more than a few workqueues executing off secondary CPU(s).
The current code does the following:
a) checks if clk is unused
b) holds lock
c) disables clk
d) unlocks

Between (a) and (b) being executed on CPU0, It is possible to
have a driver executing on CPU1 which could do a get_sync->clk_get
(and increase the use_count) of the clock which was just about
to be disabled by clk_disable_unused.

We ensure instead that the entire list traversal is protected by
the lock allowing for parent child clock traversal which could be
potentially be done by runtime operations to be safe as well.

Change-Id: Iea5201233d89b8417576df4ed9026e1c05001596
Reported-by: Todd Poynor <toddpoynor@google.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
OMAP3+: Smartreflex: Fix interrupt disable sequence

With the current interrupt disable sequence, we disable IRQENABLE
followed by clearing of IRQSTATUS. With this sequence, we see, at
times CORE domain does not hit OFF mode during cold boot because
SR modules(Core/IVA/MPU domains) are stuck 'in transition'.

After the IRQ is cleared by writing the SR_xxx_IRQENABLE_CLR ,
the SW cannot read the interrupt status from IRQSTATUS register.
SW should have cleared all IRQ completely before disabling the
module. If the SW disable the module by the MODULEMODE bit
before clearing the IRQ status, the SR module is still in the
'In transition' mode.

Hence, the right sequence we have is write to IRQSTATUS register
to clear the interrupt, then write to IRQENABLE_CLR register to
disable the interrupt to ensure that no pending interrupts exist
in the system on disable of SmartReflex AVS block.

Change-Id: Ic0e3d9960ed9511769c3c25b2c71ff1e53bcc796
Reported-by: Honda Kenji <x0092217@ti.com>
Reported-by: Maki Tanaka <m-tanaka1@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Huzefa Kankroliwala <huzefank@ti.com>
blaze_defconfig: Remove SGX driver from blaze_defconfig

SGX driver is now built outside the kernel tree as a loadable
module.

Change-Id: I99eb0fcdf46dcdf9761c411740e4b33ad5e11be9
Signed-off-by: Hemant Hariyani <hemanthariyani@ti.com>