cpufreq: interface for setting governor for a cpu

This implementation sets governor for a cpu using existing
cpufreq interfaces.

bug 871958

Change-Id: Ic4e7e2a2b0babaf1829b559b5db211666d449b86
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/97939
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
arm: tegra: sdhci: Define ddr50 clock limit

Added a new variable in sdhci platform data
which will limit the ddr50 mode clock.

Bug 967719

Change-Id: I3f55b55651362447845c2e1d5000939e3e028df6
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/100569
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
mmc: tegra: Set eMMC DDR clock based on emc clock

Set the eMMC ddr mode clock dynamically based on emc
clock rate. If ddr clock limit is specified and the emc
clock is less than max emc freq, then limit emmc ddr
clk. If not, set the max eMMC ddr clock.

Bug 967719

Change-Id: I9f70077c4ac4bb1f3e6d894fcb8420b1aba284dd
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/100579
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
arm: tegra: clock: Add tegra3 sdmmc4 EMC shared user

Adding tegra3 sdmmc4 EMC shared user in the tegra3
clock table.

Bug 967719

Change-Id: I934dcaebf664f8b1db9ea07eef07eb6f266822aa
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/100582
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: clock: Export clock minimum

Add clock minimum to debugfs.

Bug 917644

Change-Id: Ie088809829af2bdc81a969a034bf00847459f0ce
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/101555
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
media: video: tegra: add GPL v2 MODULE_LICENSE

Add MODULE_LICENSE to modules that do not advertise a license,
and therefore taint the kernel.

Bug 979176

Change-Id: I1abbfa9ca1535b39e70d8bf7aa975e2663a6e45d
Signed-off-by: Eric Brower <ebrower@nvidia.com>
Reviewed-on: http://git-master/r/100214
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
cpufreq: Don't clip PM QoS requests to old policy limits

Clipping PM QoS requests to combined old policy limits that include
both PM QoS and user policy requests creates a circular dependency.
As a result new PM QoS maximum limit is rejected if it is above
previous PM QoS minimum limit even though the new PM QoS minimum
limit has been already lowered below new PM QoS maximum limit.

Instead clip PM QoS request to the old user policy limits only.

Change-Id: Ice0a53a699e0798f07f0e32d6b8a28586fe5db0c
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/102386
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Donghan Ryu <dryu@nvidia.com>
Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Vikas Ramesh Kedigehalli <vikasr@nvidia.com>
spi: tegra: register interrupt as ONESHOT

The Tegra spi's engine is design as it generates interrupt
when any error occurs and it keep transferring data. It does
not stop the engine once error occurred and interrupt generated.
This may cause reentry of ISR as on error case, isr get called
where it clears interrupt and because it is still in progress,
it again interrupts and schedule the thread.
The second time scheduling of the isr/thread can cause the issue
in queue management and sw state.
So Making the interrupt as ONESHOT so that the interrupt will not
get schedule until the engine is reset in error case.

Change-Id: I96daaf50102aede93164c82b7f6da235d0a7fbfc
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/101547
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jui Chang Kuo <jckuo@nvidia.com>
Tested-by: Jui Chang Kuo <jckuo@nvidia.com>
i2c: tegra: Fix i2c unknown interrupt issue

writes to modules on APB bus may complete out-of-order. need
to guarantee that the write is completed by reading it back.

read I2C_INT_STATUS back right after writing the current int status
in the isr to make sure the clear operation of I2C_INT_STATUS is
done before the interrupt is re-enabled.
the same also done for DVC_STATUS.

bug 980763

Change-Id: I34f18804d530ccadf561fe1736552b6a4dd6e4ce
Signed-off-by: Ken Chang <kenc@nvidia.com>
Reviewed-on: http://git-master/r/101925
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
arm: tegra: governor:  change governor using cpufreq interface

Older code sets "conservative" governor in early-suspend
using sysfs entries.This implementation changes governor
in early-suspend using cpufreq interfaces.

bug 871958

Change-Id: I721afb6184982a063dc5f330da31f8fb88481cfd
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/100849
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: vfp: ensure preemption is disabled when enabling VFP access

The vfp_enable function enables access to the VFP co-processor register
space (cp10 and cp11) on the current CPU and must be called with
preemption disabled. Unfortunately, the vfp_init late initcall does not
disable preemption and can lead to an oops during boot if thread
migration occurs at the wrong time and we end up attempting to access
the FPSID on a CPU with VFP access disabled.

This patch fixes the initcall to call vfp_enable from a non-preemptible
context on each CPU and adds a BUG_ON(preemptible) to ensure that any
similar problems are easily spotted in the future.

originally from
http://git.kernel.org/?p=linux/kernel/git/will/linux.git;a=commit;h=468c963e0210bf8108b17cf75066f25f39cabb56

Change-Id: I26fff8abe4c18bd3291613f70d0228aa2313811a
Reported-by: Hyungwoo Yang <hwoo.yang@gmail.com>
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Reviewed-on: http://git-master/r/102315
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Conflicts:

	arch/arm/vfp/vfpmodule.c
ARM: tegra: clock: Share Tegra3 camera EMC bandwidth

Change Tegra3 camera EMC shared user mode from SHARED_FLOOR to
SHARED_BW and combine requests from ISO clients (camera and display,
which is already in SHARED_BW mode).

Bug 652739

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit f1107ea4fe229d9807c1fba79a003753d0a8be7f)

Change-Id: If5b7f578060a646df1794dde8c9be2944d88e942
Reviewed-on: http://git-master/r/103498
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
GVS: Gerrit_Virtual_Submit
ARM: tegra: clock: Account for memory BW efficiency

Account for memory efficiency when processing requests from Tegra3
EMC shared bandwidth users. Do not round requests from these users
until they are aggregated.

The respective debugfs node: /d/tegra_emc/efficiency (in %).

Bug 952739

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 86929087f68c4366d6179101eb9a6a6473a4f084)

Change-Id: I4acdd89f44de1401ce5dad8fc4936932df014458
Reviewed-on: http://git-master/r/103499
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
GVS: Gerrit_Virtual_Submit
video: tegra: dc: remove bandwidth efficiency

Remove the efficiency factor in the bandwidth calculation.
Clock API will take care off setting the right clock based factoring the
efficiency.

Change-Id: I2b549197778b5afaf1aab3cc87a84debb08172e8
Reviewed-on: http://git-master/r/91659
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/103682
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
GVS: Gerrit_Virtual_Submit
crypto: tegra-se: Use sg_next to get next sg

Use sg_next to get next sg

Bug 958431

Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>

Change-Id: I14aa7c9c551d0230b9c5b681a2699dd5355d0a6d
Reviewed-on: http://git-master/r/98449
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
ARM: tegra: dvfs: Re-factor CPU alternative dvfs

Removed alternative frequencies table from dvfs structure, and
replaced it with table pointer to facilitate future support for
multiple alternative tables. Actually supported alternative dvfs
table (Tegra3 CPU cold zone table) is not changed.

Change-Id: Ia8c1d1f2dd450f0e48685e769ca925b8e6f5b57b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/104882
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: dvfs: Alter CPU dvfs on EDP events

Extended EDP processing of cpu up/down events with calls to alter CPU
dvfs table. This is in addition to already supported changing of CPU
dvfs on EDP thermal event. For now, added calls do not actually alter
the table.

Change-Id: I1cbf2c54eeca8dea1e7b6f4c65d8dbaf563a980e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/104883
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: dvfs: Separate Tegra3 single core dvfs table

On Tegra3 added mechanism to alter dvfs table between single and
multiple CPU cores. This mechanism is dormant since no single-core
table is available yet.

Change-Id: I63bd513bd5fd7347f64c88f46974cf7fac55c419
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/105508
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: cpu: enable VDD_CPU rail before LP to G transition

When doing LP to G transition, it had a power up latency on VDD_CPU
rail. To reduce the latency, CPU_LP can trun on the VDD_CPU rail
before the LP to G transition.

Bug 930985

Change-Id: I087e185ea5aa90f309b8cafba9bc4bb7d3fc950c
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-on: http://git-master/r/93141
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>
Tested-by: Antti Miettinen <amiettinen@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
fat: Remove FAT Directory Bread message

Remove FAT Directory Bread message which is
causing timing issues.

Bug 992496

Change-Id: Ieb58e38bf8ac81f6c0558361f9f296a8e9071b33
Signed-off-by: venkata jagadish <vjagadish@nvidia.com>
Reviewed-on: http://git-master/r/105354
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>