cpufreq: Add cpu utilization statistics to aid decisions made by userspace.

Understanding system load as seen by cpufreq can help userspace
algorithms make better decisions to improve system responsiveness.
One such example would be the MP decision algorithm which mines
various system info to make decisions on hot plugging in/out
the additional cores.

CRs-fixed: 344675
Signed-off-by: Anitha Anand <anithas@codeaurora.org>
(cherry picked from commit cbeef6aafc4964c4a6cfafd26b23eaccd40804b4)

Change-Id: I7b4450ed7b3bf8196870717e1907fd93c5cfbe98
Signed-off-by: Ramakrishna Prasad N <crpn@codeaurora.org>
msm: camera: Fix the stretch issue in Camera Preview

In non zsl camera preview mode, two vfe outputs are configured as
preview and video outputs. Greater of the two is output from main
scaler and the lower one from the secondary scaler. In Camera preview
mode,
application matches preview dimensions aspect ratio to snapshot
dimensions and in camcorder mode it is matched to video.

In Current design, We have below scenarios for Non ZSL Camera Preview

Case1: Main Scaler is preview and secondary scalar is video
In this scenario no error is observed
Case2: Main scalar is video and secondary scalar is preview
In this scenario since preview output in derived from video but the
aspect ratio may not match in camera mode, so we see stretch in camera
preview.

This issue is fixed by configuring only single VFE output as per
display dimensions in Camera Preview  since the second video output
is never used

CRs-Fixed: 343884
Change-Id: I25a82b417a3ed1b28ea243c6ce988c23d5fed4a7
Signed-off-by: Nishant Pandit <npandit@codeaurora.org>
msm_fb : Disable power collapse before VSync to negate wake up latencies.

For a 16ms frame period  the CPU may go into deep power collapse.
Based on the power collapse exit latency for that low power mode,
the frame period gets extended by the latency to wake up the CPU at the
next VSYNC. This results in a user experience glitch. Adding an hrtimer
to wake up the CPU few ms before the Vsync and disabling power collapse
compensates for the extra time spent in waking up the CPU out of deep
sleep. On timer expiry, set wake lock to veto idle power collapse till
the next VSync. The wake lock is released on the next VSYNC occurrence.

CRs-fixed: 368740
Signed-off-by: Anitha Anand <anithas@codeaurora.org>
(cherry picked from commit 7a77c7ca07bbcc390967552d0973238ac48b5597)

Change-Id: Id15a3297bf444180a5d172436a186d3ea06e6529
Signed-off-by: Srivalli Oguri <oguri@codeaurora.org>
lib/memcopy: use glib version

the kernel's memcpy and memmove is very inefficient. But the
gglibversion is
quite fast, in some cases it is 10 times faster than the kernel
version. So I
introduce some memory copy macros and functions of the glglibo improve
the
kernel version's performance.

The strategy of the memory functions is:
1. Copy bytes until the destination pointer is aligned.
2. Copy words in unrolled loops.  If the source and destination are not
   aligned in the same way, use word memory operations, but shift and
merge
   two read words before writing.
3. Copy the few remaining bytes.
qt602240_ts: clear unused slots in the framework after calibration

It is possible for the state of the framework and the driver to get out
of sync resulting in "stuck" touch points from the framework's
perspective.
This seems to happen only if there are touches during the device's
calibration.  The result is a locked up touchscreen for the user.

After error cases and after calibration, send an "unused" message
(-1 for ABS_MT_TRACKING_ID) for all unused slots. This fixes the
phantom stuck points.
sched: Don't call task_group() too many times in set_task_rq(

It improves performance, especially if autogroupp is enabled.

The size of set_task_rq() was 0x180 and now it is 0xa0.

Signed-off-by: Andrew Vagin <avagin@openvz.org>
Acked-by: Paul Turner <pjt@google.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link:
http://lkml.kernel.org/r/1321020240-3874331-1-git-send-email-avagin@open
vz.org
Signed-off-by: Ingo Molnar <mingo@elte.hu>
ARM: 7011/1: Add ARM cpu topology definition

The affinity between ARM processors is defined in the MPIDR register.
We can identify which processors are in the same cluster,
and which ones have performance interdependency. We can define the
cpu topology of ARM platform, that is then used by sched_mc and
sched_smt.

The default state of sched_mc and sched_smt config is disable.
When enabled, the behavior of the scheduler can be modified with
sched_mc_power_savings and sched_smt_power_savings sysfs interfaces.

Changes since v4 :
*  Remove unnecessary parentheses and blank lines

Changes since v3 :
* Update the format of printk message
* Remove blank line

Changes since v2 :
* Update the commit message and some comments

Changes since v1 :
* Update the commit message
* Add read_cpuid_mpidr in arch/arm/include/asm/cputype.h
* Modify header of arch/arm/kernel/topology.c
* Modify tests and manipulation of MPIDR's bitfields
* Modify the place and dependancy of the config
* Modify Noop functions

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: cpu topology: modify cpu topology

Modify the CPU topology policy according to the sched_mc level and the
cortex family

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>

ARM: cpu topology: Add update_cpu_topology function

arch_update_cpu_topology function is called by the scheduler
before building its sched_domain hierarchy. Prepare the update
of the cpu topology masks in this function in addition to set
it in the the store_cpu_topology which is executed only once per cpu.

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>

ARM: cpu topology: Enable ARCH_POWER

ARM: cpu topology: Enable ARCH_POWER

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>

ARM: 7182/1: ARM cpu topology: fix warning

kernel/sched.c:7354:2: warning: initialization from incompatible
pointer type

Align cpu_coregroup_mask prototype interface with sched_domain_mask_f
typedef
use int cpu instead of unsigned int cpu

Cc: <stable@vger.kernel.org>
Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: scheduler: add a cpu_power function

Add an architecture specific function for setting cpu_power

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>

ARM: cpu topology: Modify cpu_power according to sched_mc level

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>

ARM: cpu topology: Modify cpu_power according to cpufreq

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>

ARM: cpu topology: Add asym topology flag for using cpu0 1st

Modify the CPU sched_domain flags in power save mode for using the cpu0
in ched_mc power save mode

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>

ARM: cpu topology: Adddebugss interface for cpu_power

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
lib/sha1: use the git implementation of SHA-1

For ChromiumOS, we use SHA-1 to verify the integrity of the root
filesystem.  The speed of the kernel sha-1 implementation has a major
impact on our boot performance.

To improve boot performance, we investigated using the heavily optimized
sha-1 implementation used in git.  With the git sha-1 implementation, we
see a 11.7% improvement in boot time.

10 reboots, remove slowest/fastest.

Before:

  Mean: 6.58 seconds Stdev: 0.14

After (with git sha-1, this patch):

  Mean: 5.89 seconds Stdev: 0.07

The other cool thing about the git SHA-1 implementation is that it only
needs 64 bytes of stack for the workspace while the original kernel
implementation needed 320 bytes.

Signed-off-by: Mandeep Singh Baines <msb@chromium.org>
Cc: Ramsay Jones <ramsay@ramsay1.demon.co.uk>
Cc: Nicolas Pitre <nico@cam.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: linux-crypto@vger.kernel.org
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
arm: remove "optimized" SHA1 routines

Since commit 1eb19a12bd22 ("lib/sha1: use the git implementation of
SHA-1"), the ARM SHA1 routines no longer work.  The reason? They
depended on the larger 320-byte workspace, and now the sha1 workspace is
just 16 words (64 bytes).  So the assembly version would overwrite the
stack randomly.

The optimized asm version is also probably slower than the new improved
C version, so there's no reason to keep it around.  At least that was
the case in git, where what appears to be the same assembly language
version was removed two years ago because the optimized C BLK_SHA1 code
was faster.

Reported-and-tested-by: Joachim Eastwood <manabian@gmail.com>
Cc: Andreas Schwab <schwab@linux-m68k.org>
Cc: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
oc: upped L2 freqs higher than 1.512, but lowered bus clock to 360Mhz
sched: disable GENTLTE_FAIR_SLEEPERS for better performance on Android
cpufreq: BADASS - Add cpu utilization statistics to aid decisions made by userspace.

Understanding system load as seen by cpufreq can help userspace
algorithms make better decisions to improve system responsiveness.
One such example would be the MP decision algorithm which mines
various system info to make decisions on hot plugging in/out
the additional cores.

CRs-fixed: 344675
Signed-off-by: Anitha Anand <anithas@codeaurora.org>
(cherry picked from commit cbeef6aafc4964c4a6cfafd26b23eaccd40804b4)

Change-Id: I7b4450ed7b3bf8196870717e1907fd93c5cfbe98
Signed-off-by: Ramakrishna Prasad N <crpn@codeaurora.org>
msm: cpufreq: Check cpufreq_frequency_table NULL

This is required during single kernel binary support where one target
supports cpufreq and other target is at the initial stages of bring up.
Since we cannot remove CONFIG_CPU_FREQ_MSM from the config file, but
still support the boot on both of them adding a check for targets where
table is not initialized by thea cpuu clock driver.

Change-Id: I5f52c246586f0c0378a1b2873a064ef69601e3c6
Signed-off-by: Taniya Das <tdas@codeaurora.org>
msm: cpufreq: Fix the race between dbs_refresh and hot plug.

The demand based switching responds to input events and schedules
work items on all online cpus to increase the frequency. This will
call the dbs_refresh_callback on respective cpu. If this work item
kicks in while cpu1 is progressing its way through cpufreq_add_dev,
there is a chance that work item grabs the cpu_policy_rwsem of cpu1
andreleasess that of cpu0, when add device is working through releas-
ing lock of cpu1 anrequiringng that of cpu0. This is locking out
cpu1 when it tries to come up online next time. The fix is hold the
hot plug lock while processing refresh work items.

CRs-Fixed: 362444
Change-Id: I57db7c7a9b58369bf059302896f3bf9eca2bc2bb
Signed-off-by: Krishna Vanka <kvanka@codeaurora.org>
cpufreq: allow adjusting freq when DVFS enabled
kernel:sched: LOAD_FREQ (4*HZ+61) avoids loadavg Moire

LOAD_FREQ is (5*HZ+1) to avoid high load average when idle:
http://kerneltrap.org/mailarchive/linux-kernel/2007/10/3/328568

I suggest (4*HZ+61) for a better distribution.

With some seconds based load (like SSL heartbeats)
and LOAD_FREQ at (5*HZ+1) I see Moire patterns like inverse sawtooth,
since 2 or 3 probes hit the jobs (load increases quickly),
followed by several probes missing it.

A 4.61 sec interval gives optimal distribution over when within a
second a probe is taken, as .61 is close to golden ratio phi 1.618…
(test in http://ripke.com/goldenratio.c).

12*4.61 = 55.32 secs is still close to a minute,
and 13*4.61=59.93 is even closer than the current 12*5.01=60.12
(with exponents EXP_x adjusted to a ratio of 13 instead of 12).
bcmdhd: Change packet filter settings to block multicast

A common complaint of users is that battery life on wifi
is very poor, with frequent wlan_rx_wake wake locks.

It turns out Samsung "opened up" the packet filter
settings from Gingerbread to ICS.

This makes them match the tuna configuration, minus
the filter to allow mDNS through (which lets a bunch
of other stuff through too.)

The original patch reverted to Gingerbread settings,
but it seems like the filter definitions changed
from GB to ICS.

Change-Id: Ib56d50374d86733f9a2893b5a4afbcc6cd859a75
Signed-off-by: Andrew Dodd <atd7@cornell.edu>
Test6: Reduced L2 to prevent crashes
Test8: Reduced bus speeds
Test9: Upped L2 bw to 3200