i965/gen6: implement mirroring for render path blits.

This patch adds the ability for X and Y coordinates to be negated
while doing a blorp (blit on render path), by adding X and Y
multipliers to the constant data being supplied to the WM program.

This is necessary to allow blits between a window system framebuffer
and a multisampled FBO, since window system framebuffers and FBOs use
opposite Y orientation conventions.
i965/gen6: Initial implementation of MSAA.

This patch enables MSAA for Gen6, by modifying intel_mipmap_tree to
understand multisampled buffers, adapting the rendering pipeline setup
to enable multisampled rendering, and adding multisample resolve
operations to brw_blorp_blit.cpp. Some preparation work is also
included for Gen7, but it is not yet enabled.

MSAA support is still fairly preliminary.  In particular, the
following are not yet supported:
- Fully general blits between MSAA and non-MSAA buffers.
- Formats other than RGBA8, DEPTH24, and STENCIL8.
- Centroid interpolation.
- Coverage parameters (glSampleCoverage, GL_SAMPLE_ALPHA_TO_COVERAGE,
  GL_SAMPLE_ALPHA_TO_ONE, GL_SAMPLE_COVERAGE, GL_SAMPLE_COVERAGE_VALUE,
  GL_SAMPLE_COVERAGE_INVERT).

Fixes piglit tests "EXT_framebuffer_multisample/accuracy" on
i965/Gen6.

v2: In intel_alloc_renderbuffer_storage(), quantize the requested
number of samples to the next higher sample count supported by the
hardware.  This ensures that a query of GL_SAMPLES will return the
correct value.  It also ensures that MSAA is fully disabled on Gen7
for now (since Gen7 MSAA support doesn't work yet).
Force S to zero when source not multisampled
intel: When AUB dumping, flush before emitting final bitmap command.

When we are generating an AUB dump, we make a final call to
aub_dump_bmp() as the context is being destroyed, to ensure that any
rendering performed before the application exits can be seen during a
simulation run.  However, we were doing this before flushing the batch
buffer; as a result simulation runs would not always see the effect of
all rendering commands.

This patch flushes the batch buffer just before making the final call
to aub_dump_bmp(), to ensure that all rendering is properly captured
in the final bitmap.
i965: Completely annotate the batch bo when aub dumping.

Previously, when the environment variable INTEL_DEBUG=aub was set,
mesa would simply instruct DRM to start dumping data to an .aub file,
but we would not provide DRM with any information about the format of
the data in various buffers.  As a result, a lot of the data in the
generate .aub file would be unannotated, making further data analysis
difficult.

This patch causes the entire contents of each batch buffer to be
annotated using the data in brw->state_batch_list (which was
previously used only to annotate the output of INTEL_DEBUG=bat).  This
includes data that was allocated by brw_state_batch, such as binding
tables, surface and sampler states, depth/stencil state, and so on.

The new annotation mechanism requires DRM version 2.4.34.

Reviewed-by: Eric Anholt <eric@anholt.net>
No functional change.  Pulled command packets 3DSTATE_MULTISAMPLE, 3DSTATE_SAMPLE_MASK, and STATE_BASE_ADDRESS out of gen6_blorp_emit_batch_head.
In gen7 blorp, allocate space for push constants.
Generalize sampler message write
Gen7 MSAA defines
Properly allocate interleaved format MSAA buffers on Gen7
Gen7: set up surface MSAA state properly
Add SAMPLER_MESSAGE_ARG_ZERO_INT.
Emit SI in LD message.  This allows us to map source multisampled.
Implement texture lookup order properly for Gen7.  TODO: test
Parameterize texture lookup functions so that they can store result in different places
Write manual blending code
Experimental: persample invocation
Experiment: extend encode/decode for interleaved
Experimental: turn on MSAA in Gen7
Experimental: loosen assertions to allow Gen7 MSAA