regulator: fix incorrectly cached voltage on error

In regulator_set_voltage, if _regulator_do_set_voltage returns
an error, the new voltage will still be cached.  If
regulator_set_voltage is called again with the same constraints,
it will return success, but the voltage will still be at the
old voltage.

Keep the old voltage cached if _regulator_do_set_voltage returns
and error.

Signed-off-by: Colin Cross <ccross@android.com>
Change-Id: I7c9cb3e508be92a3ec807e88f093a8e185e56b3c
netfilter: xt_qtaguid: start tracking iface rx/tx at low level

qtaguid tracks the device stats by monitoring when it goes up and down,
then it gets the dev_stats().
But devs don't correctly report stats (either they don't count headers
symmetrically between rx/tx, or they count internal control messages).

Now qtaguid counts the rx/tx bytes/packets during raw:prerouting and
mangle:postrouting (nat is not available in ipv6).

The results are in
  /proc/net/xt_qtaguid/iface_stat_fmt
which outputs a format line (bash expansion):
  ifname  total_skb_{rx,tx}_{bytes,packets}

Added event counters for pre/post handling.
Added extra ctrl_*() pid/uid debugging.

Change-Id: Id84345d544ad1dd5f63e3842cab229e71d339297
Signed-off-by: JP Abgrall <jpa@google.com>
ARM: tegra: dvfs: Update Tegra3 CPU DVFS tables

Bug 817679
Bug 841336

Change-Id: I9a9d9e7a03b64774b1d2ebd8533be85582827515
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/71755
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
modified for HTC one X kernel from nv reference by faux123
ARM: tegra: clock: Skip clocks in Tegra3 CPU set rate

Reduced Tegra3 CPU clock frequency by skipping every other clock
during clock rate change when either old or new rate is above 800MHz.
This limits max possible frequency jump when switching between main
and back-up clock sources.

Added sysfs entry for minimum time to run at reduced frequency (in
microseconds): /sys/module/tegra3_clocks/parameters/skipper_delay.
Default delay is 10us. It should be adjusted by board initialization
code based on board power distribution grid capabilities.

Bug 868692

Change-Id: I0c32a3eb91512ba610c4f842bd22ef08e9c889d0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/72682
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-on: http://git-master/r/75140
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
modified for HTC One X kernel from nv reference by faux123
arm: tegra: power: Enhance debug EDP table

Bug 844268

Change-Id: I16327668c5df0ead318753f753be1680980ad9c1
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/75030
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/75537
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
arm: tegra: power: Updated EDP table to latest spec

Changed 20C to 23C to account for hysteresis effect
Bug 844268

Change-Id: I11fca162db737e8cf81c31bf38575ecc42a730df
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/75049
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Reviewed-on: http://git-master/r/75538
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
ARM: tegra: dvfs: Add alternative dvfs frequency limits

Added an option to specify alternative dvfs frequency limits for each
tegra clock domain. These alternative limits can be applied in some
particularly extreme (e.g., slow) corner of process-temperature space
with no effect on regular limits for the rest of the space.

Bug 913884

Change-Id: I05e319b60f6dc6f4e7f15c7e677e5a3bce77f201
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/70188
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/75614
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
ARM: tegra: dvfs: Add cold zone Tegra3 CPU dvfs limits

Added alternative frequency limits for Tegra3 CPU. These limits are
applied only in the lowest CPU EDP temperature zone, and the offset
from regular Tegra3 dvfs frequencies is set at -50MHz at all scaling
voltage steps. Offset values as well as temperature threshold are to
be updated per characterization.

Bug 913884

Change-Id: Ia420f54b4c9fdc966e44d0269d45d9164d751b5f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/70189
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/75615
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
modified for HTC one X kernel from nv reference by faux123
ARM: tegra: clock: Fix Tegra3 clock locking

Added locking for non-atomic access to shared registers for the
following clocks:
- secondary PLL dividers
- audio doublers
- cml (sata/pcie) clock controls

Added locking for peripheral clocks secondary reference counting
(register access is atomic, but some clocks may share an enable bit).

Updated comments for external output clocks (shared access already
protected).

Reviewed-on: http://git-master/r/76163

Change-Id: If656bf13d966bf4590d55c5509860110efea937b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76814
Reviewed-by: Automatic_Commit_Validation_User
arm: tegra: la: Fix the register offset for G2_1

Reviewed-on: http://git-master/r/76065

Change-Id: I8eb5148399cc8a08c2f37f20927b655f3e909241
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76817
Reviewed-by: Automatic_Commit_Validation_User
tegra3: fix pll_c frequency table

tegra_pll_c_freq_table had an error in the output clock rate. This patch
fixes it so that the formula o =(i * (n / m)) holds true.

Bug 917377.

Reviewed-on: http://git-master/r/76943

Change-Id: I06cb132e9ac05dac905ef2ef0437f5278cf916e5
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77734
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
arm: tegra: Disable pll_p_out clocks by default

Disable unused pll_p_out clocks until they are
needed to reduce power.

Reviewed-on: http://git-master/r/76778

Change-Id: I16dba325fff48cc895ec115f3a4124a1d7228cee
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77736
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
arm: tegra3: change min_rate for sclk

Change the minimal rate of sclk to 12 MHz and set the lowest
frequency of sbus to be 40 MHz when display is on.

BUG 922351
Reviewed-on: http://git-master/r/76959

Change-Id: I6a2871d1cc02a19829cf397e9583122e02255f81
Signed-off-by: Wen Yi <wyi@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78010
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
modified for HTC One X kernel from nv reference by faux123
ARM: tegra: power: Set awake system CPU rate floor

Set CPU rate floor to 100MHz when the system is awake (after boot,
or on late resume). Remove the floor when the system enters early
suspend.

Bug 922351
Reviewed-on: http://git-master/r/77444

Change-Id: I68f54a3d981c1cbeac16d58d3beb6e3aa6bf190c
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78031
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
ARM: tegra: power: Report LP3 state if LP2 is not allowed

Properly report LP3 state to idle governor when LP2 entry is not
allowed and LP2 request is redirected to LP3.

Reviewed-on: http://git-master/r/77956

Change-Id: If4bdf6b635d7b40a8958dc5357903c4ea563d112
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78697
Reviewed-by: Automatic_Commit_Validation_User
ARM: tegra: power: Re-factor Tegra3 secondary CPU LP2 entry

When Tegra3 secondary CPU is entering LP2, read TWD timer state
into context structure, rather than separate local variables.

Reviewed-on: http://git-master/r/77957

Change-Id: I237eafc50a11d535b94f334631d039ba9c4bf44b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78899
Reviewed-by: Automatic_Commit_Validation_User
modified for HTC One X kernel from nv reference by faux123
ARM: tegra: power: Separate lp2 latency for G/LP CPU modes

Do not use common lp2 exit latency for Tegra3 CPU G and CPU LP modes.
Separately measure and adjust latency in each mode; restart calculation
after mode switch from the last measured latency in the target mode.

Reviewed-on: http://git-master/r/78344

Change-Id: I54803c6abf4107a578aa1fed8feaa4a419a9c07f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78902
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
ARM: tegra: power: Separate lp2 latency for secondary CPUs

Do not use common lp2 exit latency for Tegra3 secondary CPUs in
G mode. Separately measure and adjust latency on each slave CPU;
use per-cpu latency to determine target residency threshold for
entering lp2 on each CPU.

Reviewed-on: http://git-master/r/78375

Change-Id: I4470d1b4814d8f12129e21105dd952a903084f1e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78903
Reviewed-by: Automatic_Commit_Validation_User
modified for HTC One X kernel from nv reference by faux123
ARM: tegra: power: Don't over-sleep LP2 on secondary CPUs

Adjust Tegra3 secondary CPU LP2 time for exit latency to avoid
scheduler event over-sleep.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/78635
(cherry picked from commit 433a3e356a0281efb1caf9b78bb1576008a58ed2)

Change-Id: Ifd298f0a4364fe4775ae209d76b2eda24b1bfefc
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/82709
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
modified for HTC One X kernel from nv reference by faux123
ARM: tegra: power: Add external LP2 wake timers on secondary CPUs

Add an option to use external timer as Tegra3 secondary CPU wake
source from lp2 (power gated) state. This is a follow up to commit
51e6be9ce103fbeb2b73fa2a9d2b6528a6941e81 that disabled wake from
external timer, since its interrupt is registered too late - after
secondary CPU is brought on-line, and already had a chance to enter
lp2. With this commit, secondary CPU is not allowed to enter lp2 in
idle until wake timer is registered (clock-gated lp3 state is entered
instead).

External timer wake up mechanism is enabled on Tegra3 only if option
HAVE_ARM_TWD is not selected. Otherwise, continue to use local CPU
timers as lp2 wake sources.

Change-Id: Ic8c33f55e77174717bfa6525041e1263d3232dd5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/83546
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
modified for HTC One X kernel from nv reference by faux123