Add a MachinePostDominator pass

This is used in the AMDIL and R600 backends.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164029 91177308-0d34-0410-b5e6-96231b3b80d8
Removed the VMLxForwarding feature for the Cortex-A15 target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164030 91177308-0d34-0410-b5e6-96231b3b80d8
Fix a few vars that can end up being used without initialization.
The cases where no initialization happens should still be checked for logic flaws.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164032 91177308-0d34-0410-b5e6-96231b3b80d8
NewSROA: Provide a full set of operator< for ByteRanges.

MSVC8 won't compile lower_bound if one is missing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164035 91177308-0d34-0410-b5e6-96231b3b80d8
LLVM_ATTRIBUTE_USED forces emission of a function. To silence unused function warnings use LLVM_ATTRIBUTE_UNUSED.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164036 91177308-0d34-0410-b5e6-96231b3b80d8
s/__llvm_gcov_flush/__gcov_flush/g

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164040 91177308-0d34-0410-b5e6-96231b3b80d8
TableGen: Add initializer.

Keep GCC's warnings happy. It can't reason out that the state machine won't
ever hit the potentially uninitialized use in OPC_FilterValue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164041 91177308-0d34-0410-b5e6-96231b3b80d8
Fix PR13859

- Preserve the original NOutVT during casting from vector to integer by
  extracting vector elements.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164042 91177308-0d34-0410-b5e6-96231b3b80d8
whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164043 91177308-0d34-0410-b5e6-96231b3b80d8
Increase the static sizes of some SmallSets. finalizeBundle() is very frequently called for some backends, and growing into an std::set is overkill for these numbers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164044 91177308-0d34-0410-b5e6-96231b3b80d8
Make sure there is enough room for RA. getStackSize needs to be cleaned up but
we will do that when we implement the full save/restore.

Patch by Reed Kotler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164051 91177308-0d34-0410-b5e6-96231b3b80d8
PGO: preserve branch-weight metadata when simplifying two branches with a common
destination in SimplifyCondBranchToCondBranch.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164054 91177308-0d34-0410-b5e6-96231b3b80d8
Add some cases to x86 OptimizeCompare to handle DEC and INC, too.

While we are setting the earlier def to true, also make it live.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164056 91177308-0d34-0410-b5e6-96231b3b80d8
TableGen subtarget parser: Add getProcResourcesIdx().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164057 91177308-0d34-0410-b5e6-96231b3b80d8
TableGen subtarget emitter. Emit processor resources for the new machine model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164058 91177308-0d34-0410-b5e6-96231b3b80d8
TableGen subtarget emitter. Generate data tables for the new machine model.

Map the CodeGenSchedule object model onto data tables. The structure
of the data tables is defined in MC, so for convenience we include
MCSchedule.h. The alternative is maintaining a redundant copy of the
table structure definitions. Mapping the object model onto data tables
is sufficiently complicated that it should not be interleaved with
emitting source code. This avoids major problem with the backend for
itinerary generation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164059 91177308-0d34-0410-b5e6-96231b3b80d8
TableGen subtarget emitter. Format and emit data tables for the new machine model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164060 91177308-0d34-0410-b5e6-96231b3b80d8
TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164061 91177308-0d34-0410-b5e6-96231b3b80d8
TableGen subtarget emitter. Generate resolveSchedClass generated hook for resolving instruction variants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164062 91177308-0d34-0410-b5e6-96231b3b80d8
TableGen subtarget emitter. Use getSchedClassIdx.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164063 91177308-0d34-0410-b5e6-96231b3b80d8