Fix a bug in FoldSelectOpOp. Bitcast ops may change the number of vector elements, which may disagree with the select condition type.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158166 91177308-0d34-0410-b5e6-96231b3b80d8
Do not optimize the used bits of the x86 vselect condition operand, when the condition operand is a vector of 1-bit predicates.
This may happen on MIC devices.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158168 91177308-0d34-0410-b5e6-96231b3b80d8
[CMake] Adjust MSVC warnings.

Remove /Wall from LLVM_ENABLE_WARNINGS (it's useless) and promote 4239
to a level 1 warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158170 91177308-0d34-0410-b5e6-96231b3b80d8
[CMake] Order MSVC warnings numerically.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158171 91177308-0d34-0410-b5e6-96231b3b80d8
X86: optimize generated code for integer ABS

This patch will generate the following for integer ABS:
      movl    %edi, %eax
      negl    %eax
      cmovll  %edi, %eax
INSTEAD OF
      movl    %edi, %ecx
      sarl    $31, %ecx
      leal    (%rdi,%rcx), %eax
      xorl    %ecx, %eax

There exists a target-independent DAG combine for integer ABS, which converts
integer ABS to sar+add+xor. For X86, we match this pattern back to neg+cmov. 
This is implemented in PerformXorCombine.

rdar://10695237


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158175 91177308-0d34-0410-b5e6-96231b3b80d8
[CMake] Promote extension warnings to errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158176 91177308-0d34-0410-b5e6-96231b3b80d8
Teach the AsmMatcherEmitter to allow InstAlias' where the suboperands of a complex operand are called out explicitly in the asm string.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158183 91177308-0d34-0410-b5e6-96231b3b80d8
cmake: Pass the -m32 flag to modules if LLVM_BUILD_32_BITS is enabled

This was previously only done for executables and shared libraries, but not
for modules. As modules are essentially shared libraries (that need to be
dlopened explicitly), threating them the same as shared libraries seems
reasonable. This fixes the LLVM_BUILD_32_BITS build of Polly.

Contributed by: Ondra Hosek  <ondra.hosek@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158195 91177308-0d34-0410-b5e6-96231b3b80d8
Revert commit 158073 while waiting for a fix.  The issue is that reassociate
can move instructions within the instruction list.  If the instruction just
happens to be the one the basic block iterator is pointing to, and it is
moved to a different basic block, then we get into an infinite loop due to
the iterator running off the end of the basic block (for some reason this
doesn't fire any assertions).  Original commit message:

Grab-bag of reassociate tweaks.  Unify handling of dead instructions and
instructions to reoptimize.  Exploit this to more systematically eliminate
dead instructions (this isn't very useful in practice but is convenient for
analysing some testcase I am working on).  No need for WeakVH any more: use
an AssertingVH instead.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158199 91177308-0d34-0410-b5e6-96231b3b80d8
Add the PPCCTRLoops pass: a PPC machine-code-level optimization pass to form CTR-based loop branching code.

This pass is derived from the Hexagon HardwareLoops pass. The only significant enhancement over the Hexagon
pass is that PPCCTRLoops will also attempt to delete the replaced add and compare operations if they are
no longer otherwise used. Also, invalid preheader DebugLoc is not used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158204 91177308-0d34-0410-b5e6-96231b3b80d8
Fix a bug in the new PPC CTR-Loops pass.

The code which tests for an induction operation cannot assume that any
ADDI instruction will have a register operand because the operand could
also be a frame index; for example:
    %vreg16<def> = ADDI8 <fi#0>, 0; G8RC:%vreg16

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158205 91177308-0d34-0410-b5e6-96231b3b80d8
Disable the PPC CTR-Loops pass by default.

The pass itself works well, but the something in the Machine* infrastructure
does not understand terminators which define registers. Without the ability
to use the block-placement pass, etc. this causes performance regressions (and
so is turned off by default). Turning off the analysis turns off the problems
with the Machine* infrastructure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158206 91177308-0d34-0410-b5e6-96231b3b80d8
test/CodeGen/Generic/APIntLoadStore.ll: Mark as XFAIL:ppc since r157911.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158209 91177308-0d34-0410-b5e6-96231b3b80d8
BoundsChecking: add support for ConstantPointerNull. fixes a bunch of instrumentation failures in loops with reallocs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158210 91177308-0d34-0410-b5e6-96231b3b80d8
Fix Target->Codegen dependence.

Bulk move of TargetInstrInfo implementation into
TargetInstrInfoImpl. This is dirty because the code isn't part of
TargetInstrInfoImpl class, nor should it be, because the methods are
not target hooks. However, it's the current mechanism for keeping
libTarget useful outside the backend. You'll get a not-so-nice link
error if you invoke a TargetInstrInfo method that depends on CodeGen.

The TargetInstrInfoImpl class should probably be removed since it
doesn't really solve this problem.

To really fix this, we probably need separate interfaces for the
CodeGen/nonCodeGen sides of TargetInstrInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158212 91177308-0d34-0410-b5e6-96231b3b80d8
Fix a crash in APInt::lshr when shiftAmt > BitWidth.
Patch by James Benton <jbenton@vmware.com>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158213 91177308-0d34-0410-b5e6-96231b3b80d8
Sched itinerary fix: Avoid static initializers.

This fixes an accidental dependence on static initialization order that I introduced yesterday.

Thank you Lang!!!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158215 91177308-0d34-0410-b5e6-96231b3b80d8
Test case for r158160

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158218 91177308-0d34-0410-b5e6-96231b3b80d8
Enable optimization for integer ABS on X86 if Subtarget has CMOV.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158220 91177308-0d34-0410-b5e6-96231b3b80d8
Mark the PPC CTRRC and CTRRC8 register classes as non-allocatable.

Marking these classes as non-alocatable allows CTR loop generation to
work correctly with the block placement passes, etc. These register
classes are currently used only by some unused TCRETURN patterns.
In future cleanup, these will be removed.

Thanks again to Jakob for suggesting this fix to the CTR loop problem!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158221 91177308-0d34-0410-b5e6-96231b3b80d8