msm: kgsl: Detect and avoid malformed ioctl codes

Because we were using _IO_NR, one could construct a malformed ioctl
code that would avoid allocating memory yet go to a function that
expected that memory. Still use _IO_NR to index the array of ioctls,
but check that the full values match before jumping to the helper
function.

CRs-fixed: 385592
Change-Id: Ic0dedbaded469035bd0a2bb0f20fecb2a3045ca5
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
lib/memcopy: use glibc version

the kernel's memcpy and memmove is very inefficient. But the glibc version is
quite fast, in some cases it is 10 times faster than the kernel version. So I
introduce some memory copy macros and functions of the glibc to improve the
kernel version's performance.

The strategy of the memory functions is:
1. Copy bytes until the destination pointer is aligned.
2. Copy words in unrolled loops.  If the source and destination are not
   aligned in the same way, use word memory operations, but shift and merge
   two read words before writing.
3. Copy the few remaining bytes.

Signed-off-by: Miao Xie <miaox*******>
lib/string: use glibc version

the performance of memcpy and memmove of the general version is very
inefficient, this patch improved them.

Signed-off-by: Miao Xie <miaox*******>
ARM: entry: no need to increase preempt count for IRQ handlers

X-Git-Tag: v3.1-rc1~258^2~1^3~16
X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Ftorvalds%2Flinux-2.6.git;a=commitdiff_plain;h=1613cc1119ecdb1bdb950da53065e615e4c4b8db

irq_enter() and irq_exit() already take care of the preempt_count
handling for interrupts, which increment and decrement the hardirq
bits of the preempt count.  So we can remove the preempt count handing
in our IRQ entry/exit assembly, like x86 did some 9 years ago.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
mmc: msm_sdcc: Power down slots after reboot

Some reboot methods (eg. adb reboot) may not power
down SDCC slots. This can result in cards being
in unexpected states after reboot. Explicitly reset
slot voltage regulator on reboot.

CRs-Fixed: 341840
Change-Id: I8cdb52bc58e34900378af468794760653f3babad
Signed-off-by: Oluwafemi Adeyemi <aadeyemi@codeaurora.org>
diag: Fix data corruption.

Diag uses krealloc for allocating memory if number of client exceeds 15 as
krealloc doesn't initialize memory to 0 resulting in corruption of data.
This fix initializes the memory after allocation.

CRs-Fixed: 347675
Change-Id: Ide504a18adc2e1fc282c5543ec77818f346e4015
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
(cherry picked from commit 6bac272ef9b64f0830af50f1537aa18017711022)
arm: remove export for removed "optimized" SHA1 routines

This fixes the sha_transform exported twice compilation warning.
lib/sha1: use the git implementation of SHA-1

For ChromiumOS, we use SHA-1 to verify the integrity of the root
filesystem. The speed of the kernel sha-1 implementation has a major
impact on our boot performance.

To improve boot performance, we investigated using the heavily
optimized sha-1 implementation used in git. With the git
sha-1 implementation, we see a 11.7% improvement in boot time.

10 reboots, remove slowest/fastest.

Before:

Mean: 6.58 seconds Stdev: 0.14

After (with git sha-1, this patch):

Mean: 5.89 seconds Stdev: 0.07

The other cool thing about the git SHA-1 implementation is that
it only needs 64 bytes of stack for the workspace while the original
kernel implementation needed 320 bytes.

Signed-off-by: Mandeep Singh Baines <msb@chromium.org>
CC: Ramsay Jones <ramsay@ramsay1.demon.co.uk>
CC: Nicolas Pitre <nico@cam.org>
CC: Linus Torvalds <torvalds@linux-foundation.org>
CC: Herbert Xu <herbert@gondor.apana.org.au>
CC: David S. Miller <davem@davemloft.net>
CC: linux-crypto@vger.kernel.org
arm: remove "optimized" SHA1 routines

Since commit 1eb19a12bd22 ("lib/sha1: use the git implementation of
SHA-1"), the ARM SHA1 routines no longer work.  The reason? They
depended on the larger 320-byte workspace, and now the sha1 workspace is
just 16 words (64 bytes).  So the assembly version would overwrite the
stack randomly.

The optimized asm version is also probably slower than the new improved
C version, so there's no reason to keep it around.  At least that was
the case in git, where what appears to be the same assembly language
version was removed two years ago because the optimized C BLK_SHA1 code
was faster.

Reported-and-tested-by: Joachim Eastwood <manabian@gmail.com>
Cc: Andreas Schwab <schwab@linux-m68k.org>
Cc: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
msm: improve handling of DONT_MAP_HOLE_AFTER_MEMBANK0

The code to avoid mapping the hole after memory bank 0
located the start and size of this hole after running
generic initialization code which needed to convert
physical addresses to virtual ones and vice-versa
beyond this hole.

While this didn't prevent the kernel from booting, this
isn't clean, and in fact it was giving us more vmalloc
space than the config file specified (and as a result
there was less lowmem than expected).

The code to locate the hole now runs before this
initialization code.

CRs-Fixed: 352258
Signed-off-by: Larry Bassel <lbassel@codeaurora.org>
(cherry picked from commit 31a949b5c5004f017e4adfa86f4a136025acdcd4)

Change-Id: Ia80c5db63c214ab86084ef68e29429fbac622434
Signed-off-by: Zhoulu Luo <zluo@codeaurora.org>
(cherry picked from commit af20a668c96a6869d89bc9430bee748fb43f52d2)
msm: memory: Use standard cache routines

Convert custom clean, flush, and invalidate cache routines to use
standard ARM cache routines.

Change-Id: Ida0c539b89e1b6c98542221f847a9bcd7fc32a2e
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
(cherry picked from commit 29bb4d5fa7a285c8fb5d5db55225dab700b80419)

Signed-off-by: Zhoulu Luo <zluo@codeaurora.org>
board: msm7x27a: Fix the battery capacity calculation logic.

Battery capacity calculation is missing boundary checks. This
is causing capacity to be more than 100%, when battery voltage
goes below minimum operating voltage. This inturn is causing
failure to trigger graceful shutdown at low voltages. Fix is
to have the boundary checks in capacity calculation.

CRs-Fixed: 369687
Signed-off-by: Krishna Vanka <kvanka@codeaurora.org>
(cherry picked from commit b3494693e10489ae04b84e25b1c06ddee10f0973)

Change-Id: I66c008dcb28c4abb9cab3f129ec491fb0e63b5d8
Signed-off-by: Srivalli Oguri <oguri@codeaurora.org>
board: msm7x27a: Correct the operating voltage range.

As per the PMIC team right operating voltage range is 3.2 to 4.2V.
So correcting the voltage range to this. The Android framework pops
up low battery warning at 14% of the remaining baterry capacity.
With this new range 14% would be at 3.34V. So fill this voltage in
fail_safe_voltage in the board file so that target wakes up incase
it reaches this voltage when its asleep.

CRs-Fixed: 366506
Signed-off-by: Krishna Vanka <kvanka@codeaurora.org>
(cherry picked from commit 9a265e1b6b713138236e70241cbeace7b70f0878)

Change-Id: I3decbd2d2008126e14861d904cbfc72c93a2ca4a
Signed-off-by: Srivalli Oguri <oguri@codeaurora.org>