[ARM] Renaming pl190 to vic and making it linux-like vic.c for future updates.

Signed-off-by: Anup Patel <anup@brainfault.org>
[TOP] Fix symbol addresses included in the vmm.elf

With inclusion of system.o some of the symbol addresses change. To fix the same we generate another system.map and include it.

Signed-off-by: Anup Patel <anup@brainfault.org>
[TOOLS] kallsyms: portable definition of PTR and ALGN

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] Added __weak compiler attribute.

Signed-off-by: Anup Patel <anup@brainfault.org>
[TOOLS] kallsyms: Fix .align in generated .S file for 32-bit and 64-bit machines

Signed-off-by: Anup Patel <anup@brainfault.org>
[LIBS] Stacktracing framework added

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] Add cpu-specific stacktrace functions for arm32 and arm32ve

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] Updated defconfigs of all boards.

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] Dump stacktrace on vmm_panic(), BUG_ON(), and WARN_ON()

Signed-off-by: Anup Patel <anup@brainfault.org>
Merge remote-tracking branch 'upstream/master'
[CORE] Update WARN_ON() to return value of expression passed as argument.

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] Improve WARN() macro

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] GIC: Support gic initialization from device tree.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] Update PB-A8 and VExpress board support to depend totally on host device tree for initialization.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] Remove unwanted comment "ARM Board Common Options" from board/common/openconf.cfg

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] arm32: Make TTBL reserved pool size depend only on available vapool size.

Until now, TTBL reserved pool size was depend on the maximum number of VCPUs and VTLB entries per-VCPU.

In this approach, the number of free pages in vapool rapidly decreased whenever we tried to increase VTLB entries per-VCPU or maximum number of VCPUs.

Also, most of the time large part of TTBL reserved pool is unused since the approach was meant for worst case scenario where all VTLB entries belonged to different L2TBL.

This patch makes TTBL reserved pool size to be 1/8th of available vapool size.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] arm32: Introduce VTLB zoning

Until now, we implemented VTLB as set of VTLB lines and each VTLB line as set of VTLB entries.
The VTLB line was addressed based on virtual address and the VTLB entries in VTLB line were associative.
This approach tried to implement VTLB similar to cpu cache but did not scale well and only thing that worked well is a VTLB with just one line.

This patch introduces a new way of implementing VTLB called VTLB zoning.

According to VTLB zoning, we divide a VCPU VTLB into zones and each VTLB zone is a set of VTLB entiries.
The VTLB zoning is a heuristic based approach and each VTLB zone represents specific type of VTLB entires or VTLB pages.
In the new approach, we have total 350 entries divided into 3 zones: global (200 pages or entires), non-global (125 pages or entires), and virtual (25 pages or entires).
From various trials it was observed that for good performance the ratio of global entries to non-global entries should be as close to 8:5 (i.e. golden ratio).

The new VTLB approach further improves guest linux boot-time, CPU performance and memory read/write bandwidth.

Signed-off-by: Anup Patel <anup@brainfault.org>
[COMMANDS] Print host model as board name in "host info" command when possible
[ARM] arm32: Fixed arch_delay_loop_to_cycles() for real hw beagleboard.

Signed-off-by: Anup Patel <anup@brainfault.org>
Merge remote-tracking branch 'upstream/master'