Merge HTC QMR1 endeavoru-2.6.39-86aa44d
tegra: usb: host: Clean-up hsic device connection retries

usb_phy is handling conenction with hsic device. Removing
hsic conenction re-tries logic from ehci_tegra.

Bug 932606

Change-Id: I7bdea39966eb66d4cb8271d913c449dfa1ff4b2f
Signed-off-by: Seshendra Gadagottu<sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/82758
(cherry picked from commit 5e3c81372ffb2601cc9f078111b90aba03a7b1f0)
Reviewed-on: http://git-master/r/87502
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
tegra: pcie: Remove unnecessary clock operations

All these clock operations should be handled by
powergate operations.

bug 840051

Reviewed-on: http://git-master/r/66177
(cherry picked from commit 1ad8fe3e184db04063275c837e240827bda009e9)

Change-Id: I0159c6c1f64932b22b25d31d4bb1ff9d41385879
Reviewed-on: http://git-master/r/86126
Tested-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
sdhci: Don't set highspeed mode

if SDHCI_QUIRK_NO_HISPD_BIT is set in host->quirks,
don't set SDHCI_CTRL_HISPD in sdhci_host_control register.

bug 929985

Signed-off-by: Harry Hong <hhong@nvidia.com>
Reviewed-on: http://git-master/r/79933
(cherry picked from commit 194670660af90b2bb7bc0efea920332459296141)

Change-Id: I7b5f58f5078886309610e9e4cc2bad83f0788168
Reviewed-on: http://git-master/r/87704
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
video: tegra: dsi: fix DSI_PAD_CONTROL reg wr value on resume

In panel resume path DSI_PAD_CONTROL value gets calibrated,
however later on values are overwritten with bit settings
for ulpm mode.

refactor value for reg write to only change ulpm related bits.

Change-Id: I9f9713bdf376c06b0e1b9f43b3e6c9f719bbd855
Signed-off-by: Boris Suvorov <bsuvorov@nvidia.com>
Reviewed-on: http://git-master/r/85873
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
drivers: media: tegra: Fix compilation error

Change-Id: If3a7c3911add67ff9f9aecd3c2b933a8553747f3
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/87313
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: dma: Checkpatch cleanups in dma header

Fixing checkpatch error/warning in dma header.

Change-Id: I86b65c25fc4b7edac9c4f1dfaf53023eb4c56036
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/87544
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
arm: tegra: xmm: add enable_irq_wake in probe

Add enable_irq_wake in probe to enable gpio irq wake.

Bug 928950

Signed-off-by: Seongho Joo <sjoo@nvidia.com>
Reviewed-on: http://git-master/r/85972
(cherry picked from commit e81069047c14a0ab9a3e1eb5588060959d550c49)

Change-Id: Ic513179670661ddc8a75d73a0afaa6264847cb1a
Reviewed-on: http://git-master/r/87644
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: Clean kernel and I/O mappings upon LP2

There is no need to flush the complete L2 upon LP2
entry but it is necessary to clean the page table
entries needed by LP2 code sequence that has L2 off
and MMU on.

Bug 931316

Change-Id: Ice353f16d35ee24d4387e7b9b135f205c4d0ba32
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/86293
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
smp_twd: make sure timer is stopped before registering it

On secondary CPUs, the Timer Control Register is not reset
to a sane value before the timer is registered, and the TRM
doesn't seem to indicate any reset value either. In some cases,
the kernel will take an interrupt too early, depending on what
junk was present in the registers at reset time.

The fix is to set the Timer Control Register to 0 before
registering the clock_event_device and enabling the interrupt.

Problem seen on VE (Cortex A5) and Tegra.

Signed-off-by: Marc Zyngier <(address hidden)>
Change-Id: I52695f4f9a5c5e3a8973da7668b3b1352e60a80f
Reviewed-on: http://git-master/r/83085
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
video: tegra: dc: Fix the race condition of one-shot work.

Add lock to prevent race condition between cancellation of old delayed
work and schedule of new delayed work.

Bug 936337

Change-Id: I52df82e92279163841546127c72be9879ef810d0
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/86730
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
regulator: provide missing regulator_ stubs

Change-Id: I8a5329284008c03705273dfa49042fc0e07b4b3d
Signed-off-by: Mark Stadler <mastadler@nvidia.com>
Reviewed-on: http://git-master/r/87068
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
video: tegra: dc: Remove unnecessary delay in dc postsuspend

Remove unnecessary 100ms delay for primary panel since
this is needed for HDMI type only.

Bug 940012

Change-Id: Id27966fb28faa73ade3a868a9f89cadbde76e227
Signed-off-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-on: http://git-master/r/87613
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: Fix warnings for missing type forward reference

Change-Id: Ic327c7323f1d98639b20a44527d9e4a0c01d11d2
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/88113
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
ARM: tegra: power: Trim Tegra3 hotplug timings

Bug 945921
Reduce delays in going LP->G and G->Gn

(cherry picked from commit 51b7022f328d955cc4dbbf47b35403ea9c5e3a7b)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>

Change-Id: I10f68196cb64ea20461000e9b0d64999fd714395
Reviewed-on: http://git-master/r/88169
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
staging: iio: magnetometer: ak8975: Retrieve the correct i2c client data

i2c_get_clientdata() returns an object of type struct indio_dev and not
of type struct ak8975_data.

Bug 946328
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Change-Id: I5803306d6a7829cdf822d22f51fdcdb769fbea1d
Reviewed-on: http://git-master/r/88329
Reviewed-by: Mursalin Akon <makon@nvidia.com>
Reviewed-by: Shashank Sharma <shashanks@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
crypto: tegra-se: Check for valid reqeusted buffer size

Added check for valid requested process buffer size.

Bug 928454

Change-Id: I2dc389af64cb3de2f0a0a3f0bbc5057dd9bd676c
Reviewed-on: http://git-master/r/89381
Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
ARM: mm: Use CONFIG_CPA

Use CONFIG_CPA flag to allow disabling CPA code.

Change-Id: Ic6a4993dbabbef8d9847295f698887d73d81269a
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/88464
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
ARM: mm: Add config flag for CPA.

Change-Id: Ibaa40012b3954abb440882517de51ab37269942f
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/88183
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>

Conflicts:

	arch/arm/mm/Kconfig
serial: tegra: Define correct port type

When doing the cat /proc/tty/driver/tegra_uart, the serial
core display the message as
0: uart:unknown port:00000000 irq:68 tx:0 rx:0 CTS|DSR|CD|RI
4: uart:unknown port:00000000 irq:123 tx:0 rx:0 CTS|DSR|CD|RI

This is because the correct port type and iotype are not getting
set in tegra serial driver.

Setting these parameter to proper to display the information as
1: uart:TEGRA_UART mmio:0x70006040 irq:69 tx:0 rx:0 CTS|DSR|CD|RI
2: uart:TEGRA_UART mmio:0x70006200 irq:78 tx:477 rx:1603 RTS|CTS|DTR|DSR|CD|RI
3: uart:TEGRA_UART mmio:0x70006300 irq:122 tx:0 rx:0 CTS|DSR|CD|RI
4: uart:TEGRA_UART mmio:0x70006400 irq:123 tx:0 rx:0 CTS|DSR|CD|RI

bug 889724

Change-Id: Ia095623c53d1a3840c4d3759141cdf23cc2d4547
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/89122
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>