OMAP: Smartreflex: Don't break suspend/resume

This patch disables Smartreflex voltage autocompensation
(if it was enabled) while suspending and enables it back
during resume.

Now system is able to suspend and resume correctly.

Signed-off-by: Roger Quadros <rogerq@ti.com>
USB: Palmas OTG Transceiver Driver

This is the driver for the OTG transceiver built into the Palmas chip. It
handles the various USB OTG events that can be generated by cable
insertion/removal.

Signed-off-by: Graeme Gregory <gg@slimlogic.co.uk>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
OMAP4: Add Plamas support in OMAP4 Board files

Define a new config entry for Palmas and Add Palmas specific OMAP4 SDP
Board file changes.

Signed-off-by: J Keerthy <j-keerthy@ti.com>
ARM: omap5: Stub out DVFS apis till DVFS is available

Stub out DVFS apis till DVFS is available

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
ARM: omap: timer: Do not configure (wrongly) the sysc register

hwmod already does the correct SYSC configuration, so prevent the
driver from messing it up and causing wakeup issues.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
omap5: timer: Fix the build warning.

Fix the unassigned variable warning.

Signed-off-by: sricharan <r.sricharan@ti.com>
omap4: board: Add the custom configs struture in all board files.

This structure is missing in 4430 sdp and panda board files,
causing a build break.

Signed-off-by: sricharan <r.sricharan@ti.com>
ARM: omap5/hwmod: Add missing addr for iss_hwmod

Add missing addr for iss_hwmod

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
OMAP5: HWMOD: Enable hwmod for DMIC

Enable hwmod configuration in OMAP5.

TODO: Review all hwmod info for validity in OMAP5.

Signed-off-by: Ricardo Neri <ricardo.neri@ti.com>
ARM: OMAP: hwmod: Disable iss hwmod init for now

iss hwmod init crashes at boot due to the delay needed
post a softreset before the hmwod framework can read back
the SYSC register to check for reset status.
For now disable it.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
OMAP5: PM: Initialise all the clockdomains and power-domains

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
ARM: omap: scrm: Add SCRM clock nodes

Add the SCRM header and clock nodes for OMAP5.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
OMAP5: PM: Enable mercury renetion mode on CPU power domains.

In addition to the standard power-management technique, the OMAP5 MPU subsystem
also employs an SR3-APG (mercury) power-management technology to reduce leakage.
It allows for full logic and memories retention on MPU_C0 and MPU_C1 and
is controlled by the PRCM_MPU.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
OMAP CPUFREQ: Move OMAP CPUFREQ driver to mach-omap2

To use TI DVFS feature, OMAP CPUFREQ driver needs to be inside mach-omap2.

Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
OMAP3+: PM: voltage: add required debugfs interfaces

Kevin's patch:
OMAP3+: voltage: remove unneeded debugfs interface

removed ability to check the voltages in the domains.
This puts a crunch on validation we can do, hence we
re-introduce them back in

NOTE:
http://marc.info/?l=linux-omap&m=130570864519114&w=2
 - Maintainer does state that we should get regulators
 - Regulator conversion work is still many months away.
 - pulling it in here so that we can use the same.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
OMAP4: PM: VC: support configuration of i2c clks

Patch "OMAP2+: voltage: split voltage controller (VC) code into dedicated layer"
splits out the hardcoded value in the code to vc's channel init.

This patch further isolates the configuration to remove out PMIC specific
configuration as high and low times are pmic specific.

Values are updated as well based on latest TI analysis done in android k35
kernel.

As discussed in http://marc.info/?l=linux-omap&m=130569587107997&w=2
we should, if possible isolate the changes away into board, PMIC and OMAP
specific parameters, to do this, we need a better understanding of the equations
involved, which we dont at this point of time and have to depend on emperical
values. This patch however is necessary instead of the hardcoded assumptions
in place.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
OMAP4: hwmod: change sequencing

move the smartreflex and mpu device definitions to the top of the table

This facilitates any dependencies we may have later on.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-ogg-by: Vishwanath BS <vishwanath.bs@ti.com>
OMAP3+: SR Layer Cleanup [V4]

To set sr ntarget values  for all volt_domain,
volt_table is retrieved by doing a look_up of 'vdd_name'
field from omap_hwmod but voltage domain pointer does not
belong to omap_hwmod and is not used anywhere else.
As a part of voltage layer and SR Layer clean up volt
pointer is removed from omap_hwmod and added in dev
attributes of SR.

Tested on OMAP3630 SDP and OMAP4430 SDP Board

[nm@ti.com: minor modifications in sequence and GPU support]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Shweta Gulati <shweta.gulati@ti.com>
Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
Acked by: Nishanth Menon <nm@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
OMAP4: PM: VC: support configuring PMIC over I2C_SR

Many simpler PMICs such as TPS65023 as discussed in:
http://marc.info/?t=129848405600010&r=1&w=2

With a single I2C interface do still have configuration registers that
may need population. Typical being slew rate, thermal shutdown
configuration etc. These devices are typically hooked on Application
Processor's(AP) standard I2C busses. Unfortunately, when hooked on
I2C_SR, unlike the standard I2C framework, we cannot read using
Voltage controller, but we can definitely write to them. Hence
for using PMICs such as these and others such as those used with
OMAP4460, it is imperative that we provide a hook to support the
device configuration.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
OMAP3+: PM: VP: use uV for max and min voltage limits

Every PMIC has it's own eccentricities, For example, one of the
PMIC has MSB set to 1 for a specific function - voltage enable!
using an hardcoded value specific for TWL when copied over to
such an implementation causes the system to crash as the MSB bit
was 0 and the voltage got disabled!.

Instead we use actual values and depend on the convertion routines
to abstract out the eccentricities of each PMIC.

With this, we can now move the voltages to a common location in
voltage.h as they are no longer dependent on PMICs and expect the
PMIC's conversion routines to set a cap if the voltage is out of
reach for the PMIC.

Reported-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>