[PATCH] genirq: pm: Fix the enable ordering in resume
cpufreq_interactiveX.c: Some Fix Li and La
tuna_ak_defconfig: Disable X Governors - Not Usefull
cpufreq_interactiveX.c: Tuning
I've yet to find any desktop workload that benefits from anything higher than a swappiness as low as possible. Unfortunately setting it to zero can rarely lead to unexplained stalls in the VM so use 10.

-ck
The swap token is only useful in conditions of swap thrash, and actually worsens the common case by causing more swapping. Make it only have an effect when swap is more than half full.

-ck
While it may be nice to have a copy of pages on swap once written there, the more garbage we leave in the swapspace the slower any further writes and reads to and from it are. Just free swapcache whenever we can.

-ck
When kswapd is awoken due to reclaim by a running task, set the priority of kswapd to that of the calling task thus making memory reclaim cpu activity affected by nice level.

-ck
Add a background scanning timer to restore the watermarks to the pages_lots level and only call on it if kswapd has not been called upon for the last 5 seconds. This allows us to balance all zones to the more generous pages_lots watermark at a time unrelated to page allocation thus leading to lighter levels of vm load when called upon under page allocation.

Signed-off-by: Con Kolivas <kernel@kolivas.org>

The -ck patches modify mm/vmscan.c and add a timer to wake up kswapd every 5
seconds. This timer is initialized after the creation of the kswapd thread.

The kswapd() thread function calls mod_timer at the front of its infinite
service loop (to reset the timer to 5 seconds in the future). mod_timer()
includes a BUG_ON() to assert that the timer's callback function is set.

Since the wakeup timer is initialized after the kswapd thread is created, if
kswapd gets scheduled before kswapd_run() has prepared the timer, the
BUG_ON() check will throw a stack trace and immediately terminate the kswapd
thread.

This patch modifies the kswapd_run() function in mm/vmscan.c to initialize the
watermark timer before starting the kswapd thread.

Signed-off-by: Chase Venters <chase.venters at clientec.com>

-ck
When reading from large files through the generic file read functions into page cache we can detect when a file is so large that it is unlikely to be fully cached in ram. If that happens we can put it on the tail end of the inactive lru list so it can be the first thing evicted next time we need ram.

Do lots of funny buggers with underscores to preserve most of the existing
APIs.

-ck
remove unimplemented above_background_load
cpufreq: interactive: don't handle transition notification if not enabled

If multiple governors are in use then avoid processing frequency transition
notifications for CPUs on which the interactive governor is not enabled.

Change-Id: Ibd75255b921d887501a64774a8c4f62302f2d4e4
Reported-by: Francisco Franco <francisco.franco@cloudcar.com>
Signed-off-by: Todd Poynor <toddpoynor@google.com>
ARM: Set bit 22 in the PL310 (cache controller) AuxCtlr register

ARM: Set bit 22 in the PL310 (cache controller) AuxCtlr register

Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

This patch ensures that bit 22 is set in the l2x0_init() function if
PL310 and not rely on the platform code to specify it. It also modifies
the 'aux' variable only if the actual register is written so that the
final printk displays the real hardware value.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Kyungmin Park <kyungmin.park@samsung.com>
ARM: Allow ASID 0 to be allocated to tasks

ARM: Allow ASID 0 to be allocated to tasks

Now that ASID 0 is no longer used as a reserved value, allow it to be
allocated to tasks.

Reviewed-by: Frank Rowand <frank.rowand@am.sony.com>
Tested-by: Marc Zyngier <Marc.Zyngier@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
ARMv7: Flush the vectors page using the base address

ARMv7: Flush the vectors page using the base address

With the domains removal patch, the vectors page is populated using the
kernel linear mapping address. However, the flush_icache_range()
function must be called on the high vectors address because the I-cache
is allowed to have aliases (or can even be ASID-tagged VIVT). Note that
on ARMv7 processors the D-cache is non-aliasing.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: stable@vger.kernel.org
cpufreq_conservative.c: Tuning UP=95 DOWN=40 THRESHOLD + DEF=1 MAX=5 DOWN_FACTOR
cpufreq_interactive.c: TARGET_LOAD 75 + HISPEED_LOAD 85
Adjust logo_linux_clut224.ppm Experimental Ed.
Kernel Version: ak.510.42.pgm

Conflicts:
	ak-build.sh