OMAP4: OPP: Correct default ABB type for MPU OPP Turbo

Default MPU ABB type for OMAP4460/70 is following:

   OPP   | ABB type
---------+----------
 OPP50   | Bypass
 OPP100  | Bypass
 OPPTB   | Bypass
 OPPNT   | FBB
 OPPNTSB | FBB

This patch corrects default ABB type for MPU OPP Turbo for OMAP4460/70.

Change-Id: Ifc424be0b3d103f8923d2633f1a1830f2de9651f
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4460: OPP: Move ABB update for MPU OPP turbo to OPP init code

Initially ABB type update was implemented in ABB init code.
This leads to a voltage values duplication.
This patch moves ABB type detection into the OPP init code.

Change-Id: I6140dff1be0f2b9e667160da957c8e1dbabf3e8f
[taras@ti.com: remove previous implementation]
Signed-off-by: Taras Kondratiuk <taras@ti.com>
[nm@ti.com: movement of code to central opp update]
Signed-off-by: Nishanth Menon <nm@ti.com>
[mturquette@ti.com: original author]
Signed-off-by: Mike Turquette <mturquette@ti.com>
OMAP4460: OPP: update ABB for IVA OPP turbo

On 4460 all OPPs have pre-determined states for VDD_IVA's ABB LDO,
except for OPP_TURBO.  OPP_TURBO may require bypass or RBB.
depending on a characterisation data blown into eFuse
register CONTROL_STD_FUSE_OPP_DPLL_1.

Bit 21 of that register signify DPLL_IVA trim OPP_TURBO might put
IVA's ABB LDO into bypass or RBB based on this value.

This patch introduces ABB type detection into the OPP init code.

Change-Id: Ie2f49652fda667943a7a9ac76d529c6a594b8755
Signed-off-by: Nishanth Menon <nm@ti.com>
OMAP4: OPP: Make ABB type trim update more generic

Change omap4460_abb_update() with generic omap4_abb_trim_update()
So it can be used for other devices and OPPs.

Change-Id: I2390bedc439b3388eda9efbaaecf1d66f7436ab8
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4470: OPP: Update ABB type according to trim bits

Depending on a trim bits blown into eFuse register CONTROL_STD_FUSE_OPP_DPLL_1
RBB should be enabled at some MPU/IVA OPPs to reduce a leakage on OMAP4470.

 Bit #|       Name      |             Description
------+-----------------+---------------------------------------
  20  | MPU_RBB_TURBO   | 0 - RBB is trimmed and should be used.
  21  | IVA_RBB_TURBO   | 1 - RBB is not trimmed
  22  | MPU_RBB_NITRO   |
  23  | MPU_RBB_NITROSB |
  24  | IVA_RBB_NITRO   |
  25  | IVA_RBB_NITROSB |

Change-Id: Idd76e8dd2f5e55573f6dd6f7515ab57d87b14125
Signed-off-by: Taras Kondratiuk <taras@ti.com>
ION : ION buffers caching support (ION, TILER 1D buffers)

ION map is enhanced to map ion buffers as cached pages
This patch also adds IOCTLs in ION to flush and invalidate
the cached buffers
Note: TILER 2D buffers cant be mapped as cached regions to
MPU due to DMM limitation

Complete list of feature patchset (cross project dependencies)
  http://review.omapzoom.org/18390  kernel/omap
  http://review.omapzoom.org/18391  external/kernel-headers
  http://review.omapzoom.org/18392  bionic
  http://review.omapzoom.org/18393  hardware/ti/omap4xxx
  http://review.omapzoom.org/18394  hardware/ti/domx

Change-Id: I8c7c3f0375a4b3fae13f46a657d0c2eec703f72b
Signed-off-by: Kalpesh Patil <kalpeshpatil@ti.com>
Signed-off-by: Devaraj Rangasamy <dev@ti.com>
omap: iommu: program constraints based on platform data

IOMMU driver requests and releases constraints in iommu_get
and iommu_put respectively. These constraints are actually
needed only on OMAP4 and beyond for sub-systems that have
an AMMU. The current driver code has these values hard-coded
for all the chips.

A new platform data field has been added now for the constraints
values, and this allows the values to be programmed based on
the OMAP chip and also allow a unique value if needed for each
iommu instance.

The logic in IOMMU driver code is adjusted to request the
constraints only if the relevant platform data field is set.

Change-Id: Iab18cbdde1d7fa7507dbff0b9512c8577b42fefd
Signed-off-by: Subramaniam C.A <subramaniam.ca@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
omap: mailbox: add pm constraint field to mbox structure

By adding this field, the pm qos apis can be selectively applied
only if the pm constraint is set to a +ve value.

Change-Id: I3b6930e85f65f7354826813798dec76b25149370
Signed-off-by: Subramaniam C.A <subramaniam.ca@ti.com>
Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
rpmsg: omx: lower the traces level in driver open, ioctl & release

The dev_info traces in open, connect ioctl and release incur a time
penalty and affect application launch time performances. These have
been converted to dev_dbg traces.

Change-Id: Ie8ffd027c4a96bbb5cbfa634f0d661400da8dc09
Signed-off-by: Suman Anna <s-anna@ti.com>
omap: remoteproc: return -EAGAIN on a suspend time out

Support has been added on the remote processor side to allow
applications to deny the remote processor from going into a
suspend state. If one or more applications on the remote
processor request to avoid suspend, then the suspend flag is
never set by the remote processor while the request is active,
resulting in a timeout on the host side suspend code.

The runtime suspend function for remoteproc returns -EIO at
present in case of a timeout, causing the runtime pm framework
to avoid further runtime pm suspend callbacks. This is not
desired and hence the return value is changed to -EAGAIN. This
allows the runtime pm framework to retry the suspend after the
re-expiration of the timeout. This would allow the applications
on the remote processor to allow or disallow suspend independently
of the host-side.

The inital idea of having -EIO was to avoid callbacks, since a
timeout would mean that the remoteproc is in an error state.
However, if the remoteproc were in a bad state at this point, the
recovery mechanism would kick in and reload the image.

Change-Id: Ic7b9cfa220724e8024b960704598ec93854de86c
Signed-off-by: Subramaniam C.A <subramaniam.ca@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Miguel Vadillo <vadillo@ti.com>
Signed-off-by: Paul Hunt <hunt@ti.com>
OMAP4470: battery: correct temperature conversion.

TWL6032 has 12-bit ADC, TWL6030 has 10-bit ADC, battery temperature
table is calculated for the TWL6030. So battery temperature measured
correctly only for OMAP4430 and OMAP4460. Patch rejects two lower
bits of ADC channel for TWL6032 and temperature measured correctly
for all OMAP controllers.

Change-Id: I88b6f2e6fbde11fa05642d1772c797b61b2fd1ce
Signed-off-by: Oleksandr Dmytryshyn <oleksandr.dmytryshyn@ti.com>
OMAP4: omap_wdt: using of runtime PM is limited

Issues description:

1. On OMAP4 SYSCLK can't be gated, because of issue with WDTIMER2 module,
which constantly stays in "in transition" state. Value of register
CM_WKUP_WDTIMER2_CLKCTRL is always 0x00010000 in this case.
Issue occurs immediately after first idle, when hwmod framework tries
to disable WDTIMER2 functional clock - "wd_timer2_fck". After this
module falls to "in transition" state, and SYSCLK gating is blocked.

2. Due to runtime PM, watchdog timer may be completely disabled.
In current code base watchdog timer is not disabled only because of
issue 1. Otherwise state of WDTIMER2 module will be "Disabled", and there
will be no interrupts from omap_wdt. In other words watchdog will not
work at all.

Solution description:

Using of runtime PM is limited inside omap_wdt driver. Now it
is used only during probe/shutdown and suspend/resume.
As there will be no runtime PM during watchdog timer work, there will be
no attempts of enable/disable functional clock of WDTIMER2.
WDTIMER2 module will change state from "Active" to "Idle",
interrupts from omap_wdt will come normally, there will be no
blockers with SYSCLK.

Change-Id: Iaf40371b4ef2e121c042d73dc13b09a5d3b92072
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
OMAP4: Workaround the OCP synchronisation issue with 32K synctimer.

Backport from:
http://git.kernel.org/?p=linux/kernel/git/tmlind/linux-omap.git;
a=commitdiff;h=68523f4233de5f233478dde0a63047b4efb710b8

Original comment:
On OMAP4, recently a synchronisation bug is discovered by hardware
team, which leads to incorrect timer value read from 32K sync timer
IP when the IP is comming out of idle.

The issue is due to the synchronization methodology used in the SYNCTIMER IP.
The value of the counter register in 32kHz domain is synchronized to the OCP
domain register only at count up event, and if the OCP clock is switched off,
the OCP register gets out of synch until the first count up event after the
clock is switched back -at the next falling edge of the 32kHz clock.

Further investigation revealed that it applies to gptimer1 and watchdog timer2
as well which may run on 32KHz. This patch fixes the issue for all the
applicable modules.

The BUG has not made it yet to the OMAP errata list and it is applicable to
OMAP1/2/3/4/5. OMAP1/2/3 it is taken care indirectly by autodeps.

By enabling static depedency of wakeup clockdomain with MPU, as soon as MPU
is woken up from lowpower state(idle) or whenever MPU is active, PRCM forces
the OCP clock to be running and allow the counter value to be updated properly
in the OCP clock domain.

The bug is going to fixed in future OMAP versions.

Change-Id: I3c7ff239c3dcac180fcae50c1b909d417b2b8e16
Reported-Tested-by: dave.long@linaro.org
[dave.long@linaro.org: Reported the oprofile time stamp issue with synctimer
and helped to test this patch]
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
OMAP4: EMIF: Disable EMIF DDR self refresh during EMIF frequency change sequences

Errata ID: i728

Description:

If during a small window the following three events occur simultaneously:

1) The EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM SR_TIMING counter expires
2) Frequency change update is requested CM_SHADOW_FREQ_CONFIG1
   FREQ_UPDATE set to 1
3) OCP access is requested

There will be clock instability on the DDR interface.

Workaround:

Prevent event 1) while event 2) is happening: Disable the self-refresh when
self-refresh is enabled and a frequency change sequence is requested.

Change-Id: I6c216d18f2747dae8a9160669533f0f1582d3301
Signed-off-by: Jacky Cheung <jacky.cheung@ti.com>
OMAP4: McPDM: Add McPDM pins initialization

Audio Noise Issue may occur due to McPDM_DOUT floating while McPDM_CLK
is generated at the beginning of the Audio transfer to Audio IC (this
situation is created by OMAP4 McPDM module which need some time before
providing the data). A WA is to enable the internal pull-down on OMAP
McPDM_DOUT pin to avoid having the pin floating.

Pins initialization was added to make sure that McPDM pins initialized
correctly.

Change-Id: I04fe52b63bf72da0431099cbedcb7f9669ac4f27
Signed-off-by: Oleksandr Dmytryshyn <oleksandr.dmytryshyn@ti.com>
gccore: create a separate state for pulse skipping

When a blt has been committed enter a low latency power state

Change-Id: Ie94c15db496f3943317f74e20808fb8393e32734
Signed-off-by: Tony Lofthouse <a0741364@ti.com>
gccore: move power off directly to module exit

In order to remove any doubts about when off state should be achieved
move the power off to the module exit.

Change-Id: I023cb9e9f275c2b6143709dd16a4a839875e6888
Signed-off-by: Tony Lofthouse <a0741364@ti.com>
gccore: Remove Android early suspend late resume handlers

Early suspend/late resume handlers are primarily present for the purpose of getting
the screen into a low power state for Android.

On the OMAP platform the principle means of handling this is that DSSCOMP will
blank the screen.

In order to enter the lowest power state gccore should use the standard Linux
suspend/resume handlers.

Change-Id: I3dded7c5c83bc2f03048d6c8ef32fce697ab847c
Signed-off-by: Tony Lofthouse <a0741364@ti.com>
omap_gcx: enhance to provide omap operations

In order to provide the gccore driver a function to check the state
of the prcm, we will put a function pointer in the gcx platform
device.

The previous platform device entries were not used by the gccore driver.

Change-Id: I7e3f1755261d99fe022964a2a26db6ba7f42092e
Signed-off-by: Tony Lofthouse <a0741364@ti.com>
gccore: enable suspend handler and poll for idle status

When a system level suspend event occurs the gccore driver
will set the GCHOLD bit in the GC320 and wait for the module
to become idle.

Change-Id: I139b57ede6f42c8c08689eec21d2d8d919ea2038
Signed-off-by: Tony Lofthouse <a0741364@ti.com>