Simplify code a bit and make it compile better. Remove unused parameters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155428 91177308-0d34-0410-b5e6-96231b3b80d8
Remove dangling spaces. Fix some other formatting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155429 91177308-0d34-0410-b5e6-96231b3b80d8
FileCheck-ize these tests. Harden some of them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155432 91177308-0d34-0410-b5e6-96231b3b80d8
FileCheck-ize these tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155433 91177308-0d34-0410-b5e6-96231b3b80d8
FileCheck-ize tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155434 91177308-0d34-0410-b5e6-96231b3b80d8
Look for the 'Is Simulated' module flag. This indicates that the program is compiled to run on a simulator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155435 91177308-0d34-0410-b5e6-96231b3b80d8
AVX: We lower VECTOR_SHUFFLE and BUILD_VECTOR nodes into vbroadcast instructions
using the pattern (vbroadcast (i32load src)). In some cases, after we generate
this pattern new users are added to the load node, which prevent the selection
of the blend pattern. This commit provides fallback patterns which perform
in-vector broadcast (using in-vector vbroadcast in AVX2 and pshufd on AVX1).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155437 91177308-0d34-0410-b5e6-96231b3b80d8
Refactor Thumb ITState handling in ARM Disassembler to more efficiently use its vector


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155439 91177308-0d34-0410-b5e6-96231b3b80d8
AVX2: The BLENDPW instruction selects between vectors of v16i16 using an i8
immediate. We can't use it here because the shuffle code does not check that
the lower part of the word is identical to the upper part.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155440 91177308-0d34-0410-b5e6-96231b3b80d8
Add missing test cases for ARM VLD4 (single 4-element structure to all lanes)
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155444 91177308-0d34-0410-b5e6-96231b3b80d8
Add missing test cases for ARM VLD3 (single 3-element structure to all lanes)
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155453 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterPressure: A utility for computing register pressure within a
MachineInstr sequence.

This uses the new target interface for tracking register pressure
using pressure sets to model overlapping register classes and
subregisters.

RegisterPressure results can be tracked incrementally or stored at
region boundaries. Global register pressure can be deduced from local
RegisterPressure results if desired.

This is an early, somewhat untested implementation. I'm working on
testing it within the context of a register pressure reducing
MachineScheduler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155454 91177308-0d34-0410-b5e6-96231b3b80d8
misched: DAG builder support for tracking register pressure within the current scheduling region.

The DAG builder is a convenient place to do it. Hopefully this is more
efficient than a separate traversal over the same region.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155456 91177308-0d34-0410-b5e6-96231b3b80d8
misched: ignore debug values during scheduling

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155457 91177308-0d34-0410-b5e6-96231b3b80d8
misched: try (not too hard) to place debug values where they belong

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155458 91177308-0d34-0410-b5e6-96231b3b80d8
misched: DAG builder must special case earlyclobber

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155459 91177308-0d34-0410-b5e6-96231b3b80d8
cmake: new file

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155460 91177308-0d34-0410-b5e6-96231b3b80d8
AVX: Add additional vbroadcast replacement sequences for integers.
Remove the v2f64 patterns because it does not match any vbroadcast
instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155461 91177308-0d34-0410-b5e6-96231b3b80d8
Related to PR1255. Let's begin. I'll commit classes that corresponds to our latest PR1255 discussion posts in llvm-commits.

Strategy.
0. Implement new classes. Classes doesn't affect anything. They still work with ConstantInt base values at this stage.
1. Fictitious replacement of current ConstantInt case values with ConstantRangesSet. Case ranges set will still hold single value, and ConstantInt *getCaseValue() will return it. But additionally implement new method in SwitchInst that allows to work with case ranges. Currenly I think it should be some wrapper that returns either single value or ConstantRangesSet object.
2. Step-by-step replacement of old "ConstantInt* getCaseValue()" with new alternative. Modify algorithms for all passes that works with SwitchInst. But don't modify LLParser and BitcodeReader/Writer. Still hold single value in each ConstantRangesSet object. On this stage some parts of LLVM will use old-style methods, and some ones new-style.
3. After all getCaseValue() usages will removed and whole LLVM and its clients will work in new style - modify LLParser, Reader and Writer. Remove getCaseValue().
4. Replace ConstantInt*-based case ranges set items with APInt ones.

Currently we are on Zero Stage: New classes.
ConstantRangesSet.
I selected ConstantArrays as case ranges set "holder" object (it is a temporary decision, I'll explain why below). The array items are may be ConstantVectors with single item, and ConstantVectors with two items (that means single number and range respectively).
The ConstantInt will used as basic value representation. It will replaced with APInt then. Of course ConstantArray and ConstantVector will go away after ConstantInt => APInt replacement.

New class mandatory features:
- bool isSatisfies(ConstantInt *V) method (need better name?). Returns true if the given value satisfies this case.
- Case's ranges and values enumeration. In some passes we need to analize each case (SwitchLowering for example).

Factory + unified clusterify.
I also propose to implement the factory that allows to build case object with user friendly way. I called it CRSBuilder by now.
Currenly I implemented the factory that allows add,remove pairs of range+successor. It also allows add existing ConstantRangesSet decompiling it to separated ranges. Factory can emit either clusters set (single case range + successor) or the set of "ConstantRangesSet + Successor" pairs.
So you can use it either as builder for new cases set for SwitchInst, or for clusterification of existing cases set.
Just call Factory.optimize() and it emits optimized and sorted clusters collection for you!
I tested clusterification on SelectionDAGBuilder - it works fine. Don't worry it was not included in this patch. Just new classes.
Factory is a template. There are two params: SuccessorClass and IsReadonly. So you can specify what successor you need (BB or MBB). And you can also restrict your factory to use values in read-only mode (SelectionDAGBuilder need IsReadonly=true). Read-only factory couldn't build the cases ranges.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155464 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: Nuke remnant bogus code.

r154362 was supposed to delete this bit, but obviously didn't.

rdar://11305594

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155465 91177308-0d34-0410-b5e6-96231b3b80d8