MAKEALL: Fix kill_children

When building in parallel, make sure that we look up the children
based on the the actual process group id instead of just assuming
that the MAKEALL pid is the process group id.

Also ensure that logs from incomplete builds are deleted in the
process.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
MAKEALL: Add options for incremental building

--continue will allow you to <ctrl-c> the MAKEALL and pick up where
you left off.

--rebuild-errors will allow you to rebuild only those boards which
had trouble on the last run of MAKEALL, allowing you to quickly test
a simple fix on just those boards.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
lzma: update to lzma sdk 9.20

Updated code taken from latest lzma sdk release 9.20 at
http://downloads.sourceforge.net/sevenzip/lzma920.tar.bz2

This generates quite a lot of checkpatch warnings, but I guess we
need to keep the code style as is to avoid a massive job each time we
update this.

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Signed-off-by: Simon Glass <sjg@chromium.org>
cbfs: Remove mention of CREDITS files

As requested by Wolfgang, remove references to CREDITS in the CBFS
files.

Signed-off-by: Simon Glass <sjg@chromium.org>
cbfs: Add docbook template

This adds a docbook template for fs, and makes CBFS use it.

Signed-off-by: Simon Glass <sjg@chromium.org>
part: check each variable for capability calculation

In order to calculate the capability, we use the below expression to check:
((dev_desc->lba * dev_desc->blksz)>0L)
If the capability is greater than 4GB (e.g. 8GB = 8 * 1024 * 104 * 1024),
the result will overflow, the low 32bit may be zero.

Therefore, change to check each variable to fix this potential issue.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Allow CONFIG_BOARD_SIZE_LIMIT to be specified in hex

Use the printf command to convert the number in any valid format into
the expected decimal format.  The resulting errors should be printed to
stderr.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
cmd_led.c: Standardize format of help and usage info.

Current "led" help and usage info has redundancy and extraneous
newlines, tweak it to be consistent with other commands.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
README: Explain how to generate the CHANGELOG file.

Since the top-level README file refers the reader to the CHANGELOG,
it's worth mentioning how to generate it.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
add include/u-boot.lst to .gitignore

u-boot.lst is located in include directory. Update .gitignore file
accordingly.

Signed-off-by: Luka Perkov <luka@openwrt.org>
x86: gpio: Add GPIO driver for Intel ICH6 and later.

Implement <asm-generic/gpio.h> functions for Intel ICH6 and later.
Only GPIOs 0-31 are handled by this code.

Signed-off-by: Bill Richardson <wfrichar@chromium.org>

Signed-off-by: Simon Glass <sjg@chromium.org>
x86: Enable ICH6 GPIO controller for coreboot

Coreboot uses this controller to implement GPIO access.

Signed-off-by: Simon Glass <sjg@chromium.org>
x86: gpio: Add additional GPIO banks to the ICH6 driver

We can generally trust the ICH to have GPIO Bank 0 (the first 32 pins) in the
same place across all versions. This change adds two more banks, for up to
96 GPIOS.

BUT:
- Not all chipsets have the same number of GPIOs
- Not all chipsets have the same number of GPIO banks
- Not all chipsets put the additional banks at the same offset from GPIOBASE
- There so many chipset variants that it's pretty much impossible to support
  them all, or even keep track of the new ones.

So, although this adds suppport for the additional banks that seem to work
for the particular variants of CougarPoint Mobile chipsets that we've tried,
there's no chance it will support everything Intel produces. Good luck.

Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
x86: Add function to read time stamp counter

Put this function in the u-boot-x86.h header file. We could instead create
timer.h perhaps.

We support setting a base time, and reading the time relative to this base.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
x86: Enable coreboot timestamp facility support in u-boot.

This change turns on the code which allows u-boot to add
timestamps to the timestamp table created by coreboot.

Since u-boot does not use the tsc_t like structure to represent
HW counter readings, this structure is being replaced by 64 bit
integer.

The timestamp_init() function is now initializing the base timer
value used by u-boot to calculate the HW counter increments.

Timestamp facility is initialized as soon as the timestamp table
pointer is found in the coreboot table. The u-boot generated
timer events' ID will start at 1000 to clearly separate u-boot
events from coreboot events in the timer trace.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
x86: Add a CBMEM timestamp generated right before the kernel startup.

To maintain the initialization state of the timestamp facility, thesq
pointer to the CBMEM section containing the timestamp table should be
kept in the .data section (so that it is maintained across u-boot
relocation).

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
x86: Fill in the dram info using the e820 map on coreboot/x86

This way when that dram "banks" are displayed, there's some useful information
there. The number of "banks" we claim to have needs to be adjusted so that it
covers the number of RAM e820 regions we expect to have/care about.

This needs to be done after "RAM" initialization even though we always run
from RAM. The bd pointer in the global data structure doesn't automatically
point to anything, and it isn't set up until "RAM" is available since, I
assume, it would take too much space in the very constrained pre-RAM
environment.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
x86: Add basic cache operations

Add functions to enable/disable the data cache.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
x86: Provide a function to clean up just before booting a zimage

This function can be used by boards which want to do some clean-up
before booting a zImage.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
x86: Import MSR/MTRR code from Linux

Imported from Linux 3.1 with a few modifications to suit U-Boot

Signed-off-by: Simon Glass <sjg@chromium.org>