net: wireless: bcmdhd: Propagate FW failure to upper layer

Bug: 7324935

Change-Id: I944a6da8a008ec3bcaf2f5a606e15e46eebac537
Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
net: wireless: bcmdhd: Skip turning chip off if not responding

Bug: 7324935

Change-Id: I7ae2baea80c66a39b9fc9f3a640f3a999cd193eb
Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
staging:iio:events: Don't copy data to user-space with a locked spinlock.

iio_event_chrdev_read would return -EFAULT if the user-space page was
not resident.

Change-Id: I4ac5d3bc791bb503d014d9db576b9d6d522505b2
Signed-off-by: Arve Hjønnevåg <arve@android.com>
sync: refactor sync debug printing

Move driver callbacks to fill strings instead of using seq_files.  This
will allow those values to be used in a future tracepoint patch.

Change-Id: I9b706343e35b11124141fe520e520514a32003d2
Signed-off-by: Erik Gilling <konkers@android.com>
sw_sync: convert to new value_str debug ops

Change-Id: I9bad0cac1198043e04637641feb8112e2e7a9d11
Signed-off-by: Erik Gilling <konkers@android.com>
sync: add tracepoint support

Change-Id: I181326db4247009161557e45444c9b3548b83d25
Signed-off-by: Erik Gilling <konkers@android.com>
power: android-battery: Allow changing current in charging state

When a new charge source is set, enable charging and set the charging
current, unless we've paused charging due to battery full or battery
health problems.

Change-Id: I129e621c455a941e264dc431b4eb9db6a17c9f7b
Signed-off-by: Danke Xie <d.xie@sta.samsung.com>
Signed-off-by: Todd Poynor <toddpoynor@google.com>
ARM: Use TTBR1 instead of reserved context ID

On ARMv7 CPUs that cache first level page table entries (like the
Cortex-A15), using a reserved ASID while changing the TTBR or flushing
the TLB is unsafe.

This is because the CPU may cache the first level entry as the result of
a speculative memory access while the reserved ASID is assigned. After
the process owning the page tables dies, the memory will be reallocated
and may be written with junk values which can be interpreted as global,
valid PTEs by the processor. This will result in the TLB being populated
with bogus global entries.

This patch avoids the use of a reserved context ID in the v7 switch_mm
and ASID rollover code by temporarily using the swapper_pg_dir pointed
at by TTBR1, which contains only global entries that are not tagged
with ASIDs.

Reviewed-by: Frank Rowand <frank.rowand@am.sony.com>
Tested-by: Marc Zyngier <Marc.Zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
[catalin.marinas@arm.com: add LPAE support]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on ASID-capable CPUs

Since the ASIDs must be unique to an mm across all the CPUs in a system,
the __new_context() function needs to broadcast a context reset event to
all the CPUs during ASID allocation if a roll-over occurred. Such IPIs
cannot be issued with interrupts disabled and ARM had to define
__ARCH_WANT_INTERRUPTS_ON_CTXSW.

This patch changes the check_context() function to
check_and_switch_context() called from switch_mm(). In case of
ASID-capable CPUs (ARMv6 onwards), if a new ASID is needed and the
interrupts are disabled, it defers the __new_context() and
cpu_switch_mm() calls to the post-lock switch hook where the interrupts
are enabled. Setting the reserved TTBR0 was also moved to
check_and_switch_context() from cpu_v7_switch_mm().

Reviewed-by: Will Deacon <will.deacon@arm.com>
Tested-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Frank Rowand <frank.rowand@am.sony.com>
Tested-by: Marc Zyngier <Marc.Zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
ARM: Remove current_mm per-cpu variable

The current_mm variable was used to store the new mm between the
switch_mm() and switch_to() calls where an IPI to reset the context
could have set the wrong mm. Since the interrupts are disabled during
context switch, there is no need for this variable, current->active_mm
already points to the current mm when interrupts are re-enabled.

Reviewed-by: Will Deacon <will.deacon@arm.com>
Tested-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Frank Rowand <frank.rowand@am.sony.com>
Tested-by: Marc Zyngier <Marc.Zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on pre-ARMv6 CPUs

This patch removes the __ARCH_WANT_INTERRUPTS_ON_CTXSW definition for
ARMv5 and earlier processors. On such processors, the context switch
requires a full cache flush. To avoid high interrupt latencies, this
patch defers the mm switching to the post-lock switch hook if the
interrupts are disabled.

Reviewed-by: Will Deacon <will.deacon@arm.com>
Tested-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Frank Rowand <frank.rowand@am.sony.com>
Tested-by: Marc Zyngier <Marc.Zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
net: wireless: bcmdhd: Add sync for wlfc data access

Change-Id: I2269eb3c26f0a14c1e01f067ac724fbfa6a4fb7b
Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
gpu: ion: Clear GFP_WAIT flag on high order allocations

This will prevent the kernel from kicking off compaction
when higher order allocations are made.  Instead we will
get these high order allocations only if they are readily
available.

Change-Id: I5c038781ef4028c1c0a1a52b6cb549d26550a124
Signed-off-by: Rebecca Schultz Zavin <rebecca@android.com>
gpu: ion: Don't flush allocatoins that come from the page pools

Change-Id: Ib08cb2cea3b6ea4b1ebf5a1b28abe6b9374fd2bd
Signed-off-by: Rebecca Schultz Zavin <rebecca@android.com>