1. fix places where immed is used in place of imm to be consistent with
non mips16
2. fix some comments to change OPcode->EXTEND for extended instructions

Patch by Reed Kotler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158378 91177308-0d34-0410-b5e6-96231b3b80d8
sched: Avoid trivially redundant DAG edges. Take the one with higher latency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158379 91177308-0d34-0410-b5e6-96231b3b80d8
sched: fix latency of memory dependence chain edges for consistency.

For store->load dependencies that may alias, we should always use
TrueMemOrderLatency, which may eventually become a subtarget hook. In
effect, we should guarantee at least TrueMemOrderLatency on at least
one DAG path from a store to a may-alias load.

This should fix the standard mode as well as -enable-aa-sched-mi".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158380 91177308-0d34-0410-b5e6-96231b3b80d8
disable use of directive .set nomicromips
until this directive is pushed in gas to open source fsf

Patch by Reed Kotler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158381 91177308-0d34-0410-b5e6-96231b3b80d8
Clean up trailing blanks in Mips16InstrFormats.td

Patch by Reed Kotler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158382 91177308-0d34-0410-b5e6-96231b3b80d8
Eliminate struct TableGenBackend.

TableGen backends are simply written as functions now.

Patch by Sean Silva!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158389 91177308-0d34-0410-b5e6-96231b3b80d8
SimplifyCFG: fold unconditional branch to its predecessor if profitable.

This patch extends FoldBranchToCommonDest to fold unconditional branches.
For unconditional branches, we fold them if it is easy to update the phi nodes 
in the common successors.

rdar://10554090


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158392 91177308-0d34-0410-b5e6-96231b3b80d8
Add another missing 64-bit itinerary definition for the PPC A2 core.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158393 91177308-0d34-0410-b5e6-96231b3b80d8
Fix intrinsics for XOP frczss/sd instructions. These instructions only take one source register and zero the upper bits of the destination rather than preserving them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158396 91177308-0d34-0410-b5e6-96231b3b80d8
When linearizing a multiplication, return at once if we see a factor of zero,
since then the entire expression must equal zero (similarly for other operations
with an absorbing element).  With this in place a bunch of reassociate code for
handling constants is dead since it is all taken care of when linearizing.  No
intended functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158398 91177308-0d34-0410-b5e6-96231b3b80d8
It is possible for several constants which aren't individually absorbing to
combine to the absorbing element.  Thanks to nbjoerg on IRC for pointing this 
out.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158399 91177308-0d34-0410-b5e6-96231b3b80d8
Use LTO_CODEGEN_PIC_MODEL_DYNAMIC for PIE. This requirest a git version of
gold to work. Since the enum value LDPO_PIE has just been added to plugin-api.h,
use a numeric constant for now so that we don't require an unreleased
version of gold to build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158402 91177308-0d34-0410-b5e6-96231b3b80d8
*typo: Cyles changed to Cycles

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158404 91177308-0d34-0410-b5e6-96231b3b80d8
Fix building ThreadLocal.cpp with --disable-threads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158405 91177308-0d34-0410-b5e6-96231b3b80d8
Allow SROA to look at a vector type and see if the offset is out of range to be replaced with a scalar access

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158407 91177308-0d34-0410-b5e6-96231b3b80d8
Revert "Allow SROA to look at a vector type and see if the offset is out of range to be replaced with a scalar access"

This reverts commit 51786e0aaec76b973205066bd44f7f427b21969f.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158408 91177308-0d34-0410-b5e6-96231b3b80d8
Fix pattern for MKMSK instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158409 91177308-0d34-0410-b5e6-96231b3b80d8
Implement fastcc calling convention for MIPS.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158410 91177308-0d34-0410-b5e6-96231b3b80d8
Simplify CreateLoadLR and CreateStoreLR in MipsISelLowering.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158413 91177308-0d34-0410-b5e6-96231b3b80d8
Set a higher value for maxStoresPerMemcpy in MipsISelLowering.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158414 91177308-0d34-0410-b5e6-96231b3b80d8