OMAP4: smartreflex: Fix compilation warning.

OMAP4: smartreflex: Fix compilation warning.

Remove compilation warning:
arch/arm/mach-omap2/smartreflex-class1p5.c:72: warning:
'class1p5_margin' defined but not used

Change-Id: I03faf7ff027692622e3365fbf25ccef8ca89bd8c
Signed-off-by: Oleksandr Kozaruk <oleksandr.kozaruk@ti.com>
OMAP4: Clock: Force a DPLL clkdm/pwrdm ON before a relock

OMAP4: Clock: Force a DPLL clkdm/pwrdm ON before a relock

All DPLLs except USB are in ALWON powerdomain. Make sure the
clkdm/pwrdm for USB DPLL (l3init) is turned on before attempting
a DPLL relock. So, mark the database accordingly.

Without this fix, it was seen that DPLL relock fails while testing
relock in a loop of USB DPLL.

Change-Id: I52f621a2c83e3e0dc4f6c440291860b285854e12
Tested-by: Ameya Palande <ameya.palande@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
OMAP: dmtimer: Fix memory leak on dmtimer error

OMAP: dmtimer: Fix memory leak on dmtimer error

Change-Id: I858c24a21410f2c1c85b1b8b2c1fc4dc5d3c1e6d
Signed-off-by: Jared Suttles <jsuttles@motorola.com>
OMAP: dmtimer: Fix timer handling logic for non loses_context timers

OMAP: dmtimer: Fix timer handling logic for non loses_context timers

The use of the enabled flag is currently tightly coupled with the
loses_context flag on the timer struct. This change makes the enabled
flag behave more sanely without consideration of the loses_context flag.

Change-Id: I9d33bb4cc3fd7917ad493adde75cf57cb240b106
Signed-off-by: Jared Suttles <jsuttles@motorola.com>
OMAP4: PM: Handle LPDDR CLK IO errata during suspend/idle

There is a HW bug in CMD PHY which gives ISO signals as same for
both PADn and PADp on differential IO pad, because of which IO
leaks higher as pull controls are differential internally and
pull value does not match A value.
Though there is no functionality impact due to this bug, it is
seen that by disabling the pulls there is a savings ~500uA in
OSWR, but draws ~300uA more during OFF mode.

To save power during both idle/suspend following approach taken:
 1) Enable WA during boot-up.
 2) Disable WA while attempting suspend and enable during resume.

CDDS no: OMAP4460-1.0BUG00291
(OMAP official errata ID yet to be available).

From: Ambresh K <ambresh@ti.com>
Date: Fri, 20 Jan 2012 03:41:42 +0000 (+0530)
OMAP4: PM: setup initial OPP configuration

OMAP4: PM: setup initial OPP configuration

pm.c setups the initial voltage and frequencies for init devices
on bootup to be careful of invalid device configurations by
custom bootloaders. However, DVFS data structures are not aware
of these - As a result, when doing the first time scale of
a differnt device we could have a following scenario:

At boot - MPU,IVA,Core at OPP100

after pm framework has completed initialization, lets say IVA/AESS
transitions to OPP50, DVFS framework does not have information about
the OPP current frequency/voltage of IVA/MPU and sees that only
IVA is requested, moves the IVA and core to OPP50. This configuration
is invalid as MPU is currently at OPP100 and device should not have
scaled core to OPP50 without looking at OPP100 configuration of
MPU.

To resolve this, we populate the dvfs data structure with the
requisite init devices' frequency configuration by doing a
omap_device_scale.

Change-Id: Ib3048fb7fadec5adabbbcbce56c1ead026953de6
Reported-by: Hemanth V <hemanthv@ti.com>
Tested-by: Akash Choudhari <akashc@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
HACK: OMAP2+: Makefile: sequence SR earlier than idle init

HACK: OMAP2+: Makefile: sequence SR earlier than idle init

SR should be initialized in sequence before idle initialization
is done and after pm basic inits are complete. PM initialization unfortunately
is not too smart and has to depend on initcall sequencing to ensure
proper dependencies are met. instead of fixing the entire PM init
sequence(which is possible with function pointers being registered and invoked,
but needs an entire revamp of OMAP PM's infrastructure), move SR initialization
up in the chain to ensure this works.

Change-Id: I643f73168753f618ccac6fd34b135aeb93923637
Signed-off-by: Nishanth Menon <nm@ti.com>
OMAP4: PM: work around for CPU1 onlining from OFF/OSWR state on older PPA

Originally detected in OMAP4430 ES2.3 HS samples, CPU1 crashes the
device upon calling PPA service DEFAULT_POR_NS_SMP(0x25).

Rootcause showed that cache maintenance operations required to be
performed before handing over control of CPU1 to HLOS, were incomplete
and not broadcasted from CPU0 to CPU1.

Kernel workaround for this is to use WFI to put CPU1 in OFF
state if CPU0 is not ready yet (this mechanism was in place in previous
versions of this code base but was meant to address a different need).
When putting CPU1 back to off, its internal MMU descriptors are reset
and sync'd with CPU0. CPU1 is brought online by later kernel subsystems.
Note: CPU0 power state is made to OFF for both OSWR and OFF modes.

This issue has been analysed to impact all OMAP4 non GP devices.

A config flag is introduced to allow platforms and distributions to
enable/disable if PPA version requirement is not met.

From: Wenbiao Wang <wwang@ti.com>
Date: Fri, 13 Jan 2012 03:45:15 +0000 (-0600)
OMAP4: ERRATA: ARM: Fix ARM Errata 742230

Errata 742230: This Errata workaround requires bit 4 to be set in the CP15
diagnostic control register. This patch takes care of this errata fix for GP
devices at CPU init time and at the cpu_resume stage.

From: ruchika kharwar <ruchika@ti.com>
Date: Wed, 1 Feb 2012 22:01:50 +0000 (-0600)
OMAP4: ERRATA: ARM: Fix ARM Errata 751472

Errata 751472: This Errata workaround requires bit 11 to be set in the CP15
diagnostic control register. This patch takes care of this errata fix for GP
devices at CPU init time and at the cpu_resume stage.

From: ruchika kharwar <ruchika@ti.com>
Date: Wed, 1 Feb 2012 22:19:31 +0000 (-0600)
OMAP4: ERRATA: ARM: Fix ARM Errata 743622

Errata 743622: This Errata workaround requires bit 6 to be set in the CP15
diagnostic control register. This patch takes care of this errata fix for GP
devices at CPU init time and at the cpu_resume stage.

From: ruchika kharwar <ruchika@ti.com>
Date: Wed, 1 Feb 2012 22:28:41 +0000 (-0600)
OMAP4: PM: Enforce CPU0 waking from OFF/OSWR first for GP devices also

OMAP4: PM: Enforce CPU0 waking from OFF/OSWR first for GP devices also

Note:
Patch with change Id I82c5880ec2d9a98a54755dfbd01aa981cfed9852
introduced this work around by default for all HS devices using PPA
version 1.6.4 or older.

It is determined that for GP devices the same workaround should be employed.

Change-Id: I3d307d7e6a9fb4532bd3017c0a452de8f612b314
Signed-off-by: Bryan Buckley <bryan.buckley@ti.com>
Signed-off-by: Carlos Leija <cileija@ti.com>
ARM: OMAP4: Report clock module timeouts when enabling

ARM: OMAP4: Report clock module timeouts when enabling

When a clock module is enabled, we wait for the idle-status to indicate that
the module is now enabled before continuing. Although the current code returns
an error if the idle-status does not change, we do not display any warning
message to the user. So print a message if the module idle-status does not
change as expected.

Change-Id: Ia6583174ac209f78aeecefc80cd9872d899246a2
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Revert "OMAP4: smartreflex: Fix compilation warning."

This reverts commit 2cf735faf14ed7c75cf9e4e18a473f3805b725f9.
OMAP4:PM: Remove redundant SR disable call

OMAP4:PM: Remove redundant SR disable call

SR disable is getting called twice in a row. This
patch removes the redundant call.

Change-Id: I7010347a24186d6abc693270d610482a36b6c7b8
Signed-off-by: Girish S G <girishsg@ti.com>
Reported-by: Bour Vincent <v-bour@ti.com>
OMAP4: PM: Fix L3INSTR/IVAHD save/restore context logic

OMAP4: PM: Fix L3INSTR/IVAHD save/restore context logic

The L3INSTR/IVAHD contexts are restored
when MPU is going through both OSWR and OFF states
on HS/EMU devices (not only OFF state).

Change-Id: I516a9e88932485f6d77c529602647f7199fa7212
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
OMAP: PM: Fix the build error when SmartReflex is not selected

OMAP: PM: Fix the build error when SmartReflex is not selected

Fix a build error when Smart Reflex is not selected in kernel
configuration.

Corrected the api definition in header to add the omap_volt_data to
omap_sr_enable in the else of the CONFIG_OMAP_SMARTREFLEX.

Change-Id: I552c9092afcf00a9ac6f45402a2f4414890f87fc
Signed-off-by: Mohan V <mohanv@ti.com>
Regulator: TWL6030: Unmask PREQ in MASK_TRANSITION.

Regulator: TWL6030: Unmask PREQ in MASK_TRANSITION.

Based on board configuration, unmask PREQ so that on de-assertion
or assertion on PREQ{1,2,3} transition Executes ACT2SLP and
SLP2ACT sleep sequence.

By default APPs process group is unmasked, but can be overridden
through board file using struct twl4030_power_data.

Change-Id: Ib9f561c64210e5997865a4bf7a2203dca9a1d695
Signed-off-by: Ambresh K <ambresh@ti.com>
ARM: OMAP4: l2x0: Cleanup prefetch offset register setting

ARM: OMAP4: l2x0: Cleanup prefetch offset register setting

The bits [31:5] of Prefetch Offset Register are reserved in
PL310 r2p0 so they should be kept unchanged.
It's enough to set Data prefetch enable bit in PL310 auxiliary
control register to enable the feature, so setting of bit 28 of POR
is removed.
Before writing POR value, the bits [4:0] has to be cleared to remove
previous value.

Change-Id: Id5d047da0daa0c841c69d4d587d2280d2f3433f9
Signed-off-by: Konstantin Shlyakhovoy <x0155534@ti.com>
ARM: OMAP4: l2x0: Set optimized value for prefetch offset

ARM: OMAP4: l2x0: Set optimized value for prefetch offset

Tuning the value of prefetch offset register of PL310 cache controller
for OMAP4 family. The patch can give up to 4% better results in low level
benchmarks (like bw_mem at block size above 2 Mb) and up to 2% in benchmarks
imitating use cases (like Sunspider).
Note: if double line fill is enabled, the optimal value can be different.

Change-Id: Iba7b7b5950981b851c4eac4ed636ec5d8006c87b
Signed-off-by: Konstantin Shlyakhovoy <x0155534@ti.com>