Eliminate iOS-specific tail call instructions.

After register masks were introdruced to represent the call clobbers, it
is no longer necessary to have duplicate instruction for iOS.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154209 91177308-0d34-0410-b5e6-96231b3b80d8
ARMPat is equivalent to Requires<[IsARM]>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154210 91177308-0d34-0410-b5e6-96231b3b80d8
Tidy up. 80 columns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154226 91177308-0d34-0410-b5e6-96231b3b80d8
Output UTF-8-encoded characters as identifier characters into assembly
by default.

This is a behaviour configurable in the MCAsmInfo. I've decided to turn
it on by default in (possibly optimistic) hopes that most assemblers are
reasonably sane. If this proves a problem, switching to default seems
reasonable.

I'm not sure if this is the opportune place to test, but it seemed good
to make sure it was tested somewhere.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154235 91177308-0d34-0410-b5e6-96231b3b80d8
Make the test for r154235 more platform-independent with a shorter
string.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154243 91177308-0d34-0410-b5e6-96231b3b80d8
Target/X86/MCTargetDesc/X86MCAsmInfo.cpp: Enable DwarfCFI (aka DW2) on Cygming.

Cygwin-1.7 supports dw2. Some recent mingw distros support one, too.
I have confirmed test-suite/SingleSource/Benchmarks/Shootout-C++/except.cpp can pass on Cygwin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154247 91177308-0d34-0410-b5e6-96231b3b80d8
Refactor: Use positive field names in VectorizeConfig.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154249 91177308-0d34-0410-b5e6-96231b3b80d8
Fix Thumb __builtin_longjmp with integrated assembler. <rdar://problem/11203543>

The tLDRr instruction with the last register operand set to the zero register
prints in assembly as if no register was specified, and the assembler encodes
it as a tLDRi instruction with a zero immediate.  With the integrated assembler,
that zero register gets emitted as "r0", so we get "ldr rx, [ry, r0]" which
is broken.  Emit the instruction as tLDRi with a zero immediate.  I don't
know if there's a good way to write a testcase for this.  Suggestions welcome.

Opportunities for follow-up work:
1) The asm printer should complain if a non-optional register operand is set
   to the zero register, instead of silently dropping it.
2) The integrated assembler should complain in the same situation, instead of
   silently emitting the operand as "r0".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154261 91177308-0d34-0410-b5e6-96231b3b80d8
SCEV: When expanding a GEP the final addition to the base pointer has NUW but not NSW.

Found by inspection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154262 91177308-0d34-0410-b5e6-96231b3b80d8
Fix ValueTracking to conclude that debug intrinsics are safe to
speculate. Without this, loop rotate (among many other places) would
suddenly stop working in the presence of debug info. I found this
looking at loop rotate, and have augmented its tests with a reduction
out of a very hot loop in yacr2 where failing to do this rotation costs
sometimes more than 10% in runtime performance, perturbing numerous
downstream optimizations.

This should have no impact on performance without debug info, but the
change in performance when debug info is enabled can be extreme. As
a consequence (and this how I got to this yak) any profiling of
performance problems should be treated with deep suspicion -- they may
have been wildly innacurate of debug info was enabled for profiling. =/
Just a heads up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154263 91177308-0d34-0410-b5e6-96231b3b80d8
Perform partial SROA on the helper hashing structure. I really wish the
optimizers could do this for us, but expecting partial SROA of classes
with template methods through cloning is probably expecting too much
heroics. With this change, the begin/end pointer pairs which indicate
the status of each loop iteration are actually passed directly into each
layer of the combine_data calls, and the inliner has a chance to see
when most of the combine_data function could be deleted by inlining.
Similarly for 'length'.

We have to be careful to limit the places where in/out reference
parameters are used as those will also defeat the inliner / optimizers
from properly propagating constants.

With this change, LLVM is able to fully inline and unroll the hash
computation of small sets of values, such as two or three pointers.
These now decompose into essentially straight-line code with no loops or
function calls.

There is still one code quality problem to be solved with the hashing --
LLVM is failing to nuke the alloca. It removes all loads from the
alloca, leaving only lifetime intrinsics and dead(!!) stores to the
alloca. =/ Very unfortunate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154264 91177308-0d34-0410-b5e6-96231b3b80d8
Convert floating point division by a constant into multiplication by the
reciprocal if converting to the reciprocal is exact.  Do it even if inexact
if -ffast-math.  This substantially speeds up ac.f90 from the polyhedron
benchmarks.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154265 91177308-0d34-0410-b5e6-96231b3b80d8
1. Remove the part of r153848 which optimizes shuffle-of-shuffle into a new
   shuffle node because it could introduce new shuffle nodes that were not
   supported efficiently by the target.

2. Add a more restrictive shuffle-of-shuffle optimization for cases where the
   second shuffle reverses the transformation of the first shuffle.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154266 91177308-0d34-0410-b5e6-96231b3b80d8
Remove 'else' after 'if' that ends in return.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154267 91177308-0d34-0410-b5e6-96231b3b80d8
Move vinsertf128 patterns near the instruction definitions. Add AddedComplexity to AVX2 vextracti128 patterns to give them priority over the integer versions of vextractf128 patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154268 91177308-0d34-0410-b5e6-96231b3b80d8
Turn avx2 vinserti128 intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove patterns for selecting the intrinsic. Similar was already done for avx1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154272 91177308-0d34-0410-b5e6-96231b3b80d8
Allow subclasses of the ValueHandleBase to store information as part of the
value pointer by making the value pointer into a pointer-int pair with 2 bits
available for flags.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154279 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the 'Parent' pointer from the MDNodeOperand class.

An MDNode has a list of MDNodeOperands allocated directly after it as part of
its allocation. Therefore, the Parent of the MDNodeOperands can be found by
walking back through the operands to the beginning of that list. Mark the first
operand's value pointer as being the 'first' operand so that we know where the
beginning of said list is.

This saves a *lot* of space during LTO with -O0 -g flags.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154280 91177308-0d34-0410-b5e6-96231b3b80d8
FileCheckize these testcases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154281 91177308-0d34-0410-b5e6-96231b3b80d8
Formatting changes. Don't put spaces in front of some code, which only makes it look 'off'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154282 91177308-0d34-0410-b5e6-96231b3b80d8