ARM: OMAP: AM33XX: Add missing EMIF register offsets

Add a couple of missing register offsets in the EMIF
header file. While here also fix the indentation issue.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
ARM: OMAP: AM33XX: PM: Get rid of hardcoded resume address

Instead of using a harcoded resume address in the IPC registers
add a dynamically computed offset to the start of OCMC address.

Note: This approach currently assumes that the suspend-resume code
is the first block of code that is copied to internal RAM. Due to
the initcall level used by the SRAM mapping code this holds true.
Ideally the sram mapping code should provide an API for doing this.
This will be done at a later point of time when the generic SRAM
allocator gets merged in mainline kernel.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
ARM: OMAP: AM33XX: PM: Skip DDR PHY reconfiguration in resume

DDR PHY registers were earlier being reconfigured in the resume
path. This is not necessary since these registers lie in the
WKUP domain and retain their content across various low power
state. Skipping the reconfiguration will also enabling in getting
a single kernel image to work for boards with different memory
types.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
ARM: OMAP: AM33XX: PM: Save and restore EMIF registers

The EMIF configuration parameters were earlier harcoded
under the assumption that the person updating the DDR PHY
configuration values will update the EMIF parameters also.

Now that the DDR PHY reconfiguration has been dropped, this
restriction can also go away by adopting a save and restore
mechanism of these registers.

At the same time switch to macros for EMIF register offsets
to improve readability.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
ARM: OMAP: AM33XX: PM: Wait correctly for the PLLs to relock in the sleep code

The PLL relock code was incorrectly exiting the loop
before the PLLs relock. Since the PLLs relock within
a couple of A8 assembly instruction execution this went
unnoticed till now. The issue was noticed when validating
the abort path of the suspend process wherein the
incorrect check for PLL relock resulted in a lockup.

Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
ARM: OMAP: AM33XX: PM: Restore the PLLs to pre-suspend state

In some scenarios all the PLLs (especially Display) might not be
in a locked state when the suspend process starts. Trying to relock
a PLL in MN-bypass mode without a proper set of M and N values results
into the PLLs never locking and the resume process hanging. Fix this
by restoring the PLLs to the mode that they were in before the suspend
process started.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
ARM: OMAP: PM: AM33XX: Update the sleep code to handle DDR3

DDR3 devices have a reset signal which is active low. When the
system enters low power state this signal needs to be kept high
to avoid a reset and hence a loss of memory content. DDR_IO_CTRL
register in the control module gives s/w control over the reset
line. Since the reset line is left open for DDR2 devices
(some implementation might connect this but finally it becomes
a NOP), there is no harm in setting the reset pin to high even
for DDR2. This also enables us to have the same sequence for
DDR2 and DDR3 devices.

Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
usb: musb: update babble workaround fix

Resetting of usb controller also resets the tx and rx fifo addresses of
each endpoints and hence tx and rx fifo addresses need to be reconfigured.

Signed-off-by: Ravi B <ravibabu@ti.com>
usb: musb: ti81xx: print the usbss revision id during init

This is to identify the id which can help in debugging.

Signed-off-by: Ravi B <ravibabu@ti.com>
usb: musb: cppi41: enable txfifo empty interrupt logic

Fixes the txdma early completion issue as the TxFIFO empty interrupt
logic generates an interrupt when last byte from TxFIFO is
transmitted out.

The application issues fixed are -
1) The isochronous gap issue seen due to txdma early completion and
   thus a delay caused in scheduling of txdma workthread which polls
   for txfifo empty status.

2) The workthread is rescheduled once again when txfifo is empty to
   make sure any miss of transfer of the data in internal cppififo.

3) For non-isochronous tx request uses workthread to poll for txfifo
   empty status if there is possiblity of data in internal cppififo
   other wise the request is completed directly in the tx-dma isr
   function.

Signed-off-by: Ravi B <ravibabu@ti.com>
usb: musb: host: Flush txfifo only if TxPktRdy bit set

This is needed as per mentor core documents.

Signed-off-by: Ravi B <ravibabu@ti.com>
usb: musb: cppi41: use dsb() to make sure PDs are updated to memory

Before pushing the tx/rx cppi packet descriptors to respective input queues
of TX/RX DMA channels, use memory barrier dsb() to make sure the descriptors
contents are written to memory

Signed-off-by: Ravi B <ravibabu@ti.com>
usb: musb: cppi41: fix zero byte OUT issue

Fixes ZERO byte transfer in tx direction which was not being done in DMA mode.
Used PIO mode for all zero byte tx transfer.
usb: musb: host: fix for urb error handling

Fixes below two issues related urb error handling

1) Handling incomplete transfer when short packet not expected

2) Do not start next urb when current urb has failed, this is
   because stack will unlink/dequeue remaining urbs. Programming
   the next urb will endup in urb completion because of expected
   error (cause of current urb failure) interrupts and interfere
   with urb dequeue initiated by stack and cause a crash.

Signed-off-by: Ravi B <ravibabu@ti.com>
Signed-off-by: Visuvanadan Pasupathy <vichu@ti.com>
usb: musb: cppi41: txdma flushfifo fixes during channel abort

This patch fixes the flushfifo sequence during tx dma channel
abort, the txfifo should be flushed only when the TXPKTRDY bit
is set in TXCSR register.

Signed-off-by: Ravi B <ravibabu@ti.com>
usb: musb: cppi41: tx dma completion fixes

Use spinlock_irqsave/restore only during txdma completion giveback.

Signed-off-by: Ravi B <ravibabu@ti.com>
usb: musb: host: Flush RxFIFO only when RxPktRdy is set

This need to be done as per mentor core documentations.

Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
usb: musb: ti81xx: fix role switching issue

Fixing the role switching issue seen when followed steps below:

a) Configure port in OTG mode
b) Connect MSC device through micro-A-plug to std-A-receptacle
c) MSC enumerated and works fine.
d) Disconnect MSC device and let cable be connected to port
e) Now disconnect cable also
f) Connect port to host PC using micro-B plug to std-A plug.
e) PC doesn't recognise the gadget driver.
MMC: OMAP-HS: Enable HSPE bit for high speed cards.

By outputting CMD line and DAT lines at the rising edge of the SD clock,
setup timings is increased and allows reaching higher bus frequency.
This feature is activated by setting SD_HCTL[2] HSPE bit to 1. This is
required for High Speed Cards.

When card is operating at high speed, MMC/SD serial output clock is set
to >25 MHz. This patch makes use of this clock value to set HSPE.

Also, this bit will be cleared on card removal & for non-high speed
cards.

Tested on High speed cards (SDHC class 10, micro SDHC class 4) and
normal speed cards like SDHC class 4.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>