[x86 fast-isel] Rather then call llvm_unreachable() have fast-isel fall back
to Selection DAG isel.  Patch by Andrew Kaylor <andrew.kaylor@intel.com>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160055 91177308-0d34-0410-b5e6-96231b3b80d8
test commit

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160056 91177308-0d34-0410-b5e6-96231b3b80d8
PR13326: Fix a subtle edge case in the udiv -> magic multiply generator.

This caused 6 of 65k possible 8 bit udivs to be wrong.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160058 91177308-0d34-0410-b5e6-96231b3b80d8
InstrEmitter::EmitSubregNode() optimize extract_subreg in this case:

r1025 = s/zext r1024, 4
r1026 = extract_subreg r1025, 4

to a copy:
r1026 = copy r1024

This is correct. However it uses TII->isCoalescableExtInstr() which can return
true for instructions which essentially does a sext_in_reg so this can end up
with an illegal copy where the source and destination register classes do not
match. Add a check to avoid it. Sorry, no test case possible at this time.

rdar://11849816


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160059 91177308-0d34-0410-b5e6-96231b3b80d8
Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160064 91177308-0d34-0410-b5e6-96231b3b80d8
X86: Update to peephole optimization to move Movr0 before (Sub, Cmp) pair.

When Movr0 is between sub and cmp, we move Movr0 before sub if it enables
removal of Cmp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160066 91177308-0d34-0410-b5e6-96231b3b80d8
Test case for r160036.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160067 91177308-0d34-0410-b5e6-96231b3b80d8
[x86 fast-isel] Per discussion with Eric, add all cases to switch with verbose
comments.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160069 91177308-0d34-0410-b5e6-96231b3b80d8
In register classes in MipsRegisterInfo.td, list the registers in ascending
order of binary encoding.

Patch by Vladimir Medic.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160073 91177308-0d34-0410-b5e6-96231b3b80d8
In MemoryBuffer::getOpenFile() don't verify that the mmap'ed
file buffer is null-terminated.

If the file is smaller than we thought, mmap will not allow dereferencing
past the pages that are enough to cover the actual file size,
even though we asked for a larger address range.

rdar://11612916

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160075 91177308-0d34-0410-b5e6-96231b3b80d8
Fixed diff comparison.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160076 91177308-0d34-0410-b5e6-96231b3b80d8
This change removes an "initialization" warning.

Even though variable in question could not 
be initialized before use, the code was such that 
the compiler had no way of knowing that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160081 91177308-0d34-0410-b5e6-96231b3b80d8
Fixup broken doc link.  Patch by Sean Silva <silvas@purdue.edu>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160082 91177308-0d34-0410-b5e6-96231b3b80d8
Patch for Mips direct object generation.

When WriteFragmentData() case FT_align called
Asm.getBackend().writeNopData() is called, nothing
is done since Mips implementation of writeNopData just
returned "true".

For some reason this has not caused problems in 32 bit
mode, but in 64 bit mode it caused an assert when processing
multiple function units.

The test case included will assert without this patch. It
runs twice with different flags to prevent false positives
due to changes in code generation over time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160084 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: Fix optimizeCompare to correctly check safe condition.

It is safe if CPSR is killed or re-defined.
When we are done with the basic block, check whether CPSR is live-out.
Do not optimize away cmp if CPSR is live-out.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160090 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: fix typo in comments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160093 91177308-0d34-0410-b5e6-96231b3b80d8
TableGen: Location information for diagnostic.

def Pat<...>;

Results in 'record name is not a string!' diagnostic. Not the best,
but the lack of location information moves it from not very helpful
into completely useless. We're in the Record class when throwing the
error, so just add the location info directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160098 91177308-0d34-0410-b5e6-96231b3b80d8
Instcombine was transforming:
  %shr = lshr i64 %key, 3
  %0 = load i64* %val, align 8
  %sub = add i64 %0, -1
  %and = and i64 %sub, %shr
  ret i64 %and

to:
  %shr = lshr i64 %key, 3
  %0 = load i64* %val, align 8
  %sub = add i64 %0, 2305843009213693951
  %and = and i64 %sub, %shr
  ret i64 %and

The demanded bit optimization is actually a pessimization because add -1 would
be codegen'ed as a sub 1. Teach the demanded constant shrinking optimization
to check for negated constant to make sure it is actually reducing the width
of the constant.

rdar://11793464


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160101 91177308-0d34-0410-b5e6-96231b3b80d8
Update GATHER instructions to support 2 read-write operands. Patch from myself and Manman Ren.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160110 91177308-0d34-0410-b5e6-96231b3b80d8
The result type of EXTRACT_VECTOR_ELT doesn't have to match the element type of
the input vector, it can be bigger (this is helpful for powerpc where <2 x i16>
is a legal vector type but i16 isn't a legal type, IIRC).  However this wasn't
being taken into account by ExpandRes_EXTRACT_VECTOR_ELT, causing PR13220.
Lightly tweaked version of a patch by Michael Liao.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160116 91177308-0d34-0410-b5e6-96231b3b80d8