ARM: OMAP5: PM: Consolidate OMAP4 and OMAP5 PM code

OMAP5 has backward compatible PRCM block and it's programming model is mostly
same. Consolidate the OMAP4 PM code so that it can be re-used on OMAP5 deviecs.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
ARM: OMAP5: PM: Add MPUSS CSWR support.

Program CPU0, CPU1 and MPUSS powerdomians to Close Switch Retention. Unlike
OMAP4 devices, on OMAP5 based devices, MPUSS CSWR can be achieved with CPU
power domains in CSWR. ON OMAP4 based devices, CPU CSWR was not supported
in hardware.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
ARM: OMAP5: powerdomain: Rename powerdomain44xx.c to powerdomain4xxx_5xxx.c

Rename OMAP4 powerdomain44xx.c to powerdomain4xxx_5xxx.c since all the
OMAP4 power domain APIs can be re-used.

Register a seperate 'pwrdm_ops' for OMAP5 so that additional power
domain functionality can be added.

This patch is the place holder to add OMAP5 specific FORCE OFF
power domain functionality.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
ARM: OMAP5: PM: Set MPUSS-EMIF clock-domain static dependency.

With EMIF clock-domain put under hardware supervised control, memory corruption
and untraceable crashes are observed on OMAP5. This indicates that memory read/writes
are not working with EMIF being allowed to idle.

Till issue gets root-caused, the recommendation is to set MPUSS static
dependency towards EMIF clock-domain to avoid issues.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
ARM: OMAP5: PM: Enable Mercury retention mode on CPU power domains.

In addition to the standard power-management technique, the OMAP5 MPU subsystem
also employs an SR3-APG (mercury) power-management technology to reduce leakage.

It allows for full logic and memories retention on MPU_C0 and MPU_C1 and
is controlled by the PRCM_MPU.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
ARM: OMAP: powerdomains: Add FORCE OFF transition functionality

In OMAP5 and onwards, FORCE OFF mode is introduced on CPU power domains.

Supported only on CPU power domains to take care of Cortex-A15 based
design limitation. All the CPUs in a cluster transitions to low power
state together and not individually with wfi. Force OFF mode fix that
limitation and let CPU individually hit OFF mode.

While at this move the multi-line comments in power domain header file
above the respective flags.

Folded a typo fix from Vikram Pandita for the disable API.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
ARM: OMAP5: PM: Add FORCE OFF support for hot-pluggable CPUs.

On OMAP5 and onwards, FORCE OFF mode is introduced on CPU power domains.

Supported only on secondary CPU power domains to take care of
Cortex-A15 based design limitation. All the CPUs in a cluster
transitions to low power state together and not individually
with wfi. Force OFF mode fix that limitation and let CPU individually
hit OFF mode.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
ARM: OMAP5: PM: Disable Force OFF mode since it's not working reliably.

Force OFF mode isn't working reliably. CPU1 keeps looping inside ROM code
whenever issue apears.

This patch disables the FORCE OFF and to work around the normal OFF
mode for suspend , adds CPU intefrace enable code in early wakeup path.

Needs to REVISIT this issue.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
ARM: OMAP5: PM: Add MPU OSWR mode in suspend.

In MPUSS OSWR, entire CPU cluster is powered down except L2 cache memory.
For MPUSS OSWR state, both CPU's needs to be in OFF/FORCE OFF state.

ARM common kernel secondary boot path used by cpu hotplug seems to have
an issue around an integrated L2 cache handling.
Till that is being fixed, use cpu_resume() path.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
ARM: OMAP5: PM: Add L2 cache support.

When the entire MPUSS cluster is powered down, L2 cache looses it's content
and hence while targetting such a state, l2 cache needs to be flushed.

Add the necessary support in the low power code support and update the
SAR RAM layout used for it.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
ARM: OMAP5: hwmod: Add the missing USB hwmod data

Adding the missing data for USB hwmod. This has to be fixed in the
autogen scripts finally. Fixing them manually for now.

Signed-off-by: sricharan <r.sricharan@ti.com>
ARM: OMAP5: hwmod: Add missing RESET flag for GPIO 7/8 hwmod

The RESET flag is missing from the autogen data for
GPIO 7/8. So add this manually for now.

Signed-off-by: sricharan <r.sricharan@ti.com>
ARM: OMAP5: hwmod: Fix unipro data manually

The clock data generated for unipro modules is not correct. This causes
a warning during boot. Fix it manually for now.

Signed-off-by: sricharan <r.sricharan@ti.com>
ARM: OMAP4: hwmod: add EMIF hw mod data

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
ARM: OMAP5: hwmod: add emif hwmod data

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
ARM: omap5/clock: Fix divider range for dpll H post dvidiers

DPLL hxy post dividers have a divider range from 1 to 63 instead of
1 to 31.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
ARM: omap: clock: Add missing DPLL x2 clock nodes

This patch extends the OMAP5 clock data to include
various x2 clock nodes between DPLL and HS dividers as the
clock framework skips a x2 while calculating the dpll locked
frequency.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
ARM: omap: clock: Remove modulemode control from clock fw

Modulemode control is completely handled in hwmod fw. Having it in
clock fw is redundant, so remove it.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
ARM: omap: clock: Fix all missing clksel associations for div and mux clks

Most of the divider and mux clock nodes have missing clksel
associations, along with other neccesary struct clk fields like
init, clksel_reg, clksel_mask and correct recalc.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
ARM: omap: clock: Fix modeling of the 'tricky' abe_iclk

abe_iclk is derived from aess_fclk, but is always half of abe_clk.
This is difficult to model in the current clock framework, because
of the implicit internal divider which is set to 1 if the aess_fclk
divider is set to 2 and vice versa.
Hence model it as a child of abe_clk with a fixed divider of 2.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>