thermal: msm_tsens: Add memory barriers

Change-Id: I3a5ee441be8c20c19515e60c2c21d96581fba1bf
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
msm: rpm: add barriers after write

Ensure RPM registers are written before the next operation.

Change-Id: If0830dd20a8cb680ba0d9cf3c10cd5000cb40ff6
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
msm: peripheral-reset: Use __raw_readl()/writel()

Also wait for PLL8 to enable before switching the modem to source
off of it and add appropriate memory barriers.

Change-Id: Ie104b97ae650ec8ed5eb7d2c7c722fdc724b5f9f
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
hw_random: Use memory barriers

Change-Id: I8a59e8eead9594607433e084d5aefd2a388457c1
Signed-off-by: John Howe <jhowe@codeaurora.org>
msm: spm: Add barriers to flush writing to SPM registers

Ensure that SPM registers are written to before returning from
functions.

(Cherry-picked from 8f9218956013752b2fbca905fdf2cd8c11886282)

Change-Id: Idb3db582704017e0548884a9a300d3677c99f76e
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
msm: watchdog: add barriers where appropriate

Change-Id: I5be3442f6987c9089483bb71f70582588c80d5c4
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
msm: pm2: Add 'dsb' calls after every writel functions.

Add 'dsb' macros after every  writel function. These 'dsb's
make sure that all the writes must be flushed to memory before next
instruction got executed after the dsb.

Change-Id: Ic98417368e450dbed195110ad74aedb7aa3697bf
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
qup_i2c: Add necessary memory barriers.

Driver programs a few registers that are not in the same 1K region as
others. Memory barriers are added to ensure proper ordering and
that the writes have gone through before exiting return-paths.

Change-Id: I492fef38c7f3b23e11492b31d73e17d25269eafb
Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>
msm: proc_comm: Add memory barriers

Add memory barriers to proc_comm to ensure proper ordering
of memory transactions.

Change-Id: I2aadfe04b8c4c0bc94041ddd9fd7253cd89312b3
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
crypto: Add dsb() to ensure IO access

Change-Id: I5dac6d7dfa90b380041ed42b026143aa69dcadc3
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
msm: smd: Add memory barriers

Add memory barriers needed for inter-processor
synchronization.

Change-Id: I0e1010d4804d8772976d5769f1e3753f634272ac
Signed-off-by: Eric Holmberg <eholmber@codeaurora.org>
msm: kgsl: Turn on clocks before power rails.

This is required by the modem clock team for 7x30 variants.
Order should not matter on other targets.

(cherry picked from commit 8747f87dd5beb62e93f7a155652af78e902b8a88)

Change-Id: Ib09060c2642a8b531cec834bdc9c673cfde13a4a
CRs-Fixed: 283746
Signed-off-by: Lucille Sylvester <lsylvest@codeaurora.org>
msm: restart: Add barriers where appropriate

Change-Id: I8ce2ba07ea3481d2ba156263700a8a169a5d060f
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
msm: timer: add barriers where appropriate

Change-Id: I31d08159ff67a2b2a65a337d8f74e1f4ac27aa67
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
msm: dma: add barriers where appropriate

Change-Id: Ic95f96155358dd5d1055201c9e57dc3f726a6d74
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
msm: dsps: Add dsb() for IO operation ordering.

Add dsb() after writel() to make sure write is commited
before the function returns.

Change-Id: I1208de71c71c43ae04b6332f11877e237b174c18
Signed-off-by: Amir Samuelov <amirs@codeaurora.org>
Revert "ashmem: Use different flush routine for ashmem"

This reverts commit f1b0e26a229834fd883af95ff9302cc04fb1e67e.

Signed-off-by: Jessica Gonzalez <jgaona@codeaurora.org>
Revert "ashmem: Fix flush routine of ashmem"

This reverts commit 9770b152fc240bc7e8ddd7d25df779940b1a77a3.

Signed-off-by: Jessica Gonzalez <jgaona@codeaurora.org>
Revert "msm: kgsl: Turn on clocks before power rails."

This reverts commit d1df9e272fff36a533f649195d0adbfbb0563327.

Change-Id: Ibb339ac89b584d097efff5c14c4150e5fe6659f7
Signed-off-by: Praveena Pachipulusu <pveena@codeaurora.org>
msm: 8660: Add TLBIMVAIS workaround

On ScorpionMP targets, the TLBIMVAIS instruction can, under
certain conditions, result in a faulty ASID broadcast,
necessitating the use of the TLBIMVAAIS instruction
instead.

Change-Id: Ica7a95a21a816424c86c59a0585c495a02aa0cac
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>