video: msm_fb: Increase display timeout to 2 seconds

One second time out for no frame update, as in current implementation,
does not allow CABL to reach minimum backlight level possible because
histograms dont get generated after one second. So increase time out
period to two seconds which seem to be sufficient for complete black to
complete white and vice versa transitions.

CRs-Fixed: 370804
Change-Id: I0712924d669abcb820654cd6ca5f7da37bed57e6
Signed-off-by: Pravin Tamkhane <pravint@codeaurora.org>
Signed-off-by: Carl Vanderlip <carlv@codeaurora.org>
msm_fb: display: Update mdp clock counter for unsuccessful probes

If a panel probe does not succeed, call mdp_clk_ctrl to maintain
mdp_clk_cnt counter else mismatch in counter results in mdp clock
to never go off in cases like suspend-resume.

CRs-Fixed: 385560
Change-Id: I4ca54b051af98e823dc7f3ff7b9bcb960532c7e8
Signed-off-by: Mayank Chopra <makchopra@codeaurora.org>
msm_fb: Display: Fix Dithering issue for rgb565 format

Using RGB888 as source format and rgb565 as destination pixel format,
will cause image corruption on the display. Fix this issue by
setting the destination format as RGB888 in MDP and DSI controller
pixel format as RGB565 for DSI specific panels.

CRs-Fixed: 377484
Change-Id: If58976ee9cd4825efb39437170e54796fa2213e0
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
msm_fb: display: Set timing generator after register flush

Timing generator was getting started before the register flush.
Stale values were sometimes causing IOMMU page faults on bootup.

Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
Change-Id: Ia671c3603e383af94197a23a8e5e5f32274a9978
msm: kgsl: Faster GPU hang detection

Check global GPU status registers in intervals of 2 seconds,
if the registers did not change after 2 seconds trigger a hang.
When there is an actual GPU hang and GPU is stalled, this reduces
the current hang detection time from 10 seconds to 2 seconds.
Faster GPU hang detection reduces the overall time to recover
from GPU hang.

CRs-fixed: 384922
Signed-off-by: Tarun Karra <tkarra@codeaurora.org>
(cherry picked from commit 3335f14d31f5078f1de12774e08e1321e40d093a)

Change-Id: I57f363364eb76056cc65cf9ae9d686a8dad5283d
Signed-off-by: Sridhar Gujje <sgujje@codeaurora.org>
Signed-off-by: Tarun Karra <tkarra@codeaurora.org>
msm: kgsl: Create a separate pagetable for priv bank of IOMMU

The IOMMU registers should only be accessed by priv bank. Create a separate
pagetable for priv bank and map the IOMMU registers to only this pagetable.
This is only supported for devices which can use the priv bank for
performing in stream pagetable switches.

CRs-fixed: 380834
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
(cherry picked from commit 19ca4a6cec18c35d8e2dc1cbde68f636341b5f5e)

Change-Id: I13026b8999dd882f3e4eb02997fa99645ba8b5fa
Signed-off-by: Sridhar Gujje <sgujje@codeaurora.org>
msm: kgsl: Add idle after writing SMMU ASID register

Add an idle for synchronization after writing the SMMU ASID register.

CRs-fixed: 380834
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
(cherry picked from commit be39728459a2b7a9c0a5b1faf11e7406976ddcc7)

Change-Id: I143d045cd94d575b59da6fe6d8f1ccef71d16e69
Signed-off-by: Sridhar Gujje <sgujje@codeaurora.org>
msm: kgsl: For IOMMU only decide to flush when memory is unmapped

In case of IOMMU memory needs to only be flushed when it is
unmapped and not mappped. Also, when an application is running
the number of unmaps would in most cases be less than number of
maps, so this way the number of flushes wil be fewer.

CRs-fixed: 380834
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
(cherry picked from commit 0c811269372d83d18538c74ace76554ac77ce933)

Change-Id: I7ae96adab7b336221fc6bd4e6e085180122c79e3
Signed-off-by: Sridhar Gujje <sgujje@codeaurora.org>
msm: kgsl: Remove additional idle commands

Remove unneeded idle commands from the command stream when updating
pagetables and doing TLB flushes.  Ths cuts down on the number of
commands in the ringbuffer during switches.

CRs-Fixed: 380834
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
(cherry picked from commit 5462907f72ddcc7d337ce9431d54428c8dc486eb)

Change-Id: Id930be772075f5ac099046544c80266c5fc03a07
Signed-off-by: Ram Kumar Chakravarthy Chebathini <rcheba@codeaurora.org>
msm_fb: display: fix page fault during supend/resume

There has VG1 pipe commit (pan display) happen after system
suspended. This left VG1 strill staged up at mdp mixer. Once timing
generator is enabled at resume, VG1 pipe start fetching contents from
address 0 sicne VG1 has not yet be configured. This cause page fault.
This patch has sanity check at system suspend to make sure no any pipe
stage up at mixer after suspend.

Change-Id: Idcf974ceb4afe2a3ec55b9603b700fa497f84045
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>

Conflicts:

	drivers/video/msm/mdp4_overlay_dsi_cmd.c
	drivers/video/msm/mdp4_overlay_dsi_video.c
	drivers/video/msm/mdp4_overlay_dtv.c
	drivers/video/msm/mdp4_overlay_lcdc.c
msm_fb: display: alloc/free writeback buffer done at do_blt()

To avoid double freeing writeback at end of blt mode, let
both alloc and free writeback buffer done at do_blt().

Change-Id: Ida5d24589c19be8f6f655eca6add00badca356b2
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>