now really: smartassv2, no clue why it didnt compile before
board/endeavoru: sensors fix debug section mismatch
board/pcie: fix debug section mismatch
Staging: android: fixed 80 characters warnings in lowmemorykiller.c

This patch fixes some 80 chatacters limit warnings in the lowmemorykiller.c file

Signed-off-by: Marco Navarra <fromenglish@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

Conflicts:

	drivers/staging/android/lowmemorykiller.c
cpufreq/ondemand: add early suspend/late resume drivers and tune 2-phase

add early suspend/late resume drivers to hot plug/unplug 2nd cpu depending
screen on/off to further reduce power consumption during screen off.

tuned two-phase to use 80% of max freq.
CPUfreq ondemand: update sampling rate without waiting for next sampling

When a new sampling rate is shorter than the current one, (e.g., 1 sec
--> 10 ms) regardless how short the new one is, the current ondemand
mechanism wait for the previously set timer to be expired.

For example, if the user has just expressed that the sampling rate
should be 10 ms from now and the previous was 1000 ms, the new rate may
become effective 999 ms later, which could be not acceptable for the
user if the user has intended to speed up sampling because the system is
expected to react to CPU load fluctuation quickly from __now__.

In order to address this issue, we need to cancel the previously set
timer (schedule_delayed_work) and reset the timer if resetting timer is
expected to trigger the delayed_work ealier.

Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>

Conflicts:

	drivers/cpufreq/cpufreq_ondemand.c
cpufreq: Ondemand - dynamic change of sampling rate based on screen on/off

using early_suspend/late_resume drivers to 2x min_sampling rate while screen
is off to reduce frequency transitions in hope to reduce power consumption
further

Conflicts:

	drivers/cpufreq/cpufreq_ondemand.c
ARM: tegra: dvfs: Update Tegra3 CPU DVFS tables

Bug 817679
Bug 841336

Change-Id: I9a9d9e7a03b64774b1d2ebd8533be85582827515
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/71755
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
modified for HTC one X kernel from nv reference by faux123
ARM: tegra: dvfs: Add alternative dvfs frequency limits

Added an option to specify alternative dvfs frequency limits for each
tegra clock domain. These alternative limits can be applied in some
particularly extreme (e.g., slow) corner of process-temperature space
with no effect on regular limits for the rest of the space.

Bug 913884

Change-Id: I05e319b60f6dc6f4e7f15c7e677e5a3bce77f201
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/70188
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/75614
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
ARM: tegra: dvfs: Add cold zone Tegra3 CPU dvfs limits

Added alternative frequency limits for Tegra3 CPU. These limits are
applied only in the lowest CPU EDP temperature zone, and the offset
from regular Tegra3 dvfs frequencies is set at -50MHz at all scaling
voltage steps. Offset values as well as temperature threshold are to
be updated per characterization.

Bug 913884

Change-Id: Ia420f54b4c9fdc966e44d0269d45d9164d751b5f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/70189
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/75615
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
modified for HTC one X kernel from nv reference by faux123
tegra3: fix pll_c frequency table

tegra_pll_c_freq_table had an error in the output clock rate. This patch
fixes it so that the formula o =(i * (n / m)) holds true.

Bug 917377.

Reviewed-on: http://git-master/r/76943

Change-Id: I06cb132e9ac05dac905ef2ef0437f5278cf916e5
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77734
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
tegra:dvfs: fix white space issue
Revert "ARM: tegra: dvfs: Set Tegra3 VDD_CORE min to 1.1V"

This reverts commit db462754240e2ee6cf85e1253b1475a330ea0dfe -
temporary work-around for bug 870300 is no longer needed.

Change-Id: I3b76c01eef89cd80134210926e6623f0494626dd
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/89874
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
ARM: tegra: dvfs: Add Tegra3 x7 CPU dvfs entries

Bug 841336
Reviewed-on: http://git-master/r/76912

Change-Id: I2806c8e4f08af49edf57f00a43438b1503d6aedb
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78706
Reviewed-by: Automatic_Commit_Validation_User
ARM: tegra: dvfs: correct LCD frequency for 1V

Bug 841336

Reviewed-on: http://git-master/r/82996
(cherry picked from commit 5850c8f4968fd7acbb22e377a56a476e37ac5117)

Change-Id: I61d5c1576a6f5caf82b3efec2123c47eb64889b2
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/88865
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
cpufreq: ondemand tweak dbs_refresh_callback values for 2 cpus

raise from 880MHz to 1.1GHz
tegra: cpu-tegra3: adjust balanced level from 75 to 65
tegra: custom user voltage control

initial implementation inspired by coolbho3k's custom voltage control for
galaxy nexus (OMAP4460)

also added some Processor ID debugging code to properly identify tegra3
variants