xtensa: make DoubleExceptionVector literals fit the gap

Manually load references to exc_table from the explicit literal in order
to fit DoubleExceptionVector.literals into the available 16-byte gap
before DoubleExceptionVector.text in the absence of link time
relaxation. Without this fix DoubleExceptionVector.literal section
overlaps DoubleExceptionVector.text section in the linked vmlinux image.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: turn off ld relaxation

Sometimes ld for xtensa fails to link vmlinux with the following
message:

	dangerous relocation: call8: call target out of range

This is believed to be relaxation logic issue. See the following thread
for more details:

http://old.nabble.com/xtensa-fsf-ld%3A-dangerous-relocation%3A-call8%3A-call-target-out-of-range-td34168172.html

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: properly fix missing compiler barrier in simcall

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: ISS: add BASE_BAUD definition to serial.h

This fixes the following build error in allyesconfig:

drivers/tty/serial/8250/8250_early.c: In function 'parse_options':
drivers/tty/serial/8250/8250_early.c:160:18: error: 'BASE_BAUD' undeclared (first use in this function)

Reported-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: provide DMA_ERROR_CODE definition

This fixes the following allmodconfig build error:

drivers/uio/uio_dmem_genirq.c:95:18: error: 'DMA_ERROR_CODE' undeclared (first use in this function)
drivers/uio/uio_dmem_genirq.c:238:18: error: 'DMA_ERROR_CODE' undeclared (first use in this function)
make[3]: *** [drivers/uio/uio_dmem_genirq.o] Error 1

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: fix ccount_read prototype

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: fix build warning for arch/xtensa/mm/tlb.c

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: Add config files for Diamond 233L - Rev C processor variant

The Diamond 233L processor is a pre-configured Xtensa processor tailored
for Linux application.

Signed-off-by: Pete Delaney <piet@tensilica.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa WIP: add Three Core HiFi-2 MX Variant.

Signed-off-by: Pete Delaney <piet@tensilica.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: clean up boot make rules

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: add U-Boot image support (uImage).

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: add IRQ domains support

IRQ domains provide a mechanism for conversion of linux IRQ numbers to
hardware IRQ numbers and vice versus. It is used by OpenFirmware for
linking device tree objects to their respective interrupt controllers.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: add device trees support

Device trees allow specification of hardware topology and device
parameters at runtime instead of hard-coding them in platform setup
code. This allows running single binary kernel on a range of compatible
boards.

New boot parameters tag BP_TAG_FDT is allocated and a pointer to flat
device tree is passed in it.

Note that current interrupt mapping scheme uses single cell for
interrupt identification. That means that IRQ numbers used in DTS must
be CPU internal IRQ numbers, not external. It is possible to extend
interrupt identification to two cells, and use second cell to tell
external IRQ numbers form internal. That would allow to use single DTS
on multiple boards with different mapping of external IRQ numbers.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: add support for the XTAVNET boards

The Avnet LX60/LX110/LX200 board is an FPGA board that can be configured with
an Xtensa processor and an OpenCores Ethernet device.

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: add xtavnet DTS

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: dispatch medium-priority interrupts

Add rudimentary support for dispatching medium-priority interrupts,
that is, interrupts of priority levels 2 to EXCM_LEVEL.
This change does not introduce interrupt nesting:  all interrupts are
kept locked (up to level EXCM_LEVEL) during interrupt handling.
This of course is expected to change at some point in the future.

Signed-off-by: Marc Gauthier <marc@tensilica.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>