i965: Parameterize HiZ code to prepare for adding blitting.

This patch groups together the parameters used by the HiZ functions
into a new data structure, brw_hiz_resolve_params, rather than passing
each parameter individually between the HiZ functions.  This data
structure is a subclass of brw_blorp_params, which represents the
parameters of a general-purpose blit or resolve operation.  A future
patch will add another subclass for blits.

In addition, this patch generalizes the (width, height) parameters to
a full rect (x0, y0, x1, y1), since blitting operations will need to
be able to operate on arbitrary rectangles.  Also, it renames several
of the HiZ functions to reflect the expanded role they will serve.

v2: Rename brw_hiz_resolve_params to brw_hiz_op_params.  Move
gen{6,7}_blorp_exec() functions back into gen{6,7}_blorp.h.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
i965: split gen{6,7}_blorp_exec functions into manageable chunks.

This patch splits up the gen6_blorp_exec and gen7_blorp_exec
functions, which were very long, into simple component functions.
With a few exceptions, there is one function per state packet.

This will allow blit functionality to be added without significantly
complicating the code.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>

v2: Rename the functions gen{6,7}_emit_wm_disable() to
gen{6,7}_emit_wm_config() (since the WM is not actually disabled
during HiZ ops; it simply doesn't have a program).  Also, on gen7,
split out the configration of 3DSTATE_PS to a separate function
gen7_emit_ps_config().
i965: Expose surface setup internals for use by blits.

This patch exposes the functions brw_get_surface_tiling_bits and
gen7_set_surface_tiling, so that they can be re-used when setting up
surface states in gen6_blorp.cpp and gen7_blorp.cpp.
i965/gen6+: Add code to perform blits on the render path ("blorp").

This patch expands the "blorp" component to be able to perform blits
as well as HiZ resolves.  The new blitting code is located in
brw_blorp_blit.cpp.  This includes the necessary fragment shader code
to look up pixels in the source buffer (which is configured as a
texture) and output them to the destination buffer (which is
configured as the render target).

Most of the time the fragment shader code is simple and
straightforward, since it merely has to apply a coordinate offset,
read from the texture, and write to the render target.  However, in
the case of blitting stencil buffers, things are more complicated,
since the GPU stores stencil data using W tiling, and W tiling is not
supported for textures or render targets.  So, we set up the stencil
buffers as Y tiled, and emit fragment shader code that adjusts the
coordinates to account for the difference between W and Y tiling.
Furthermore, since a rectangular region in W tiling does not
necessarily correspond to a rectangular region in Y tiling, we widen
the rectangle primitive to the nearest tile boundary and have the
fragment shader "kill" any pixels that don't fall inside the actual
desired destination rectangle.

All of this is a necessary prerequisite for implementing MSAA, since
we'll need to be able to blit between multisample color, depth, and
stencil buffers and their non-multisampled counterparts, and none of
the existing blitting mechanisms support multisampling.

In addition, the new blitting code should speed up operations where we
previously fell back to software rasterization, such as blitting of
stencil buffers.  The current fallback sequence is: first we try to do
a blit using the hardware blitting engine.  If that fails we try to do
a blit using the render path.  If that also fails then we do the blit
using a meta-op (which may or may not fall back to software
rasterization).

Note that blitting using the render path has some limitations at the
moment: it only supports a few formats, and it doesn't support
clipping or scissoring.  These limitations will be addressed in future
patch series.

v2:
- Add the code that configures the WM program to
  gen{6,7}_emit_wm_config() and gen7_emit_ps_config() rather than
  creating separate ...enable() functions.
- Call intel_prepare_render before determining which miptrees we are
  blitting from/to, because it may cause miptrees to be reallocated.
- Allow the blit to mirror X and/or Y coordinates.
- Disable blorp blits on Gen7 for now, since they aren't working yet.
i965/gen6: Initial implementation of MSAA.

This patch enables MSAA for Gen6, by modifying intel_mipmap_tree to
understand multisampled buffers, adapting the rendering pipeline setup
to enable multisampled rendering, and adding multisample resolve
operations to brw_blorp_blit.cpp. Some preparation work is also
included for Gen7, but it is not yet enabled.

MSAA support is still fairly preliminary.  In particular, the
following are not yet supported:
- Fully general blits between MSAA and non-MSAA buffers.
- Formats other than RGBA8, DEPTH24, and STENCIL8.
- Centroid interpolation.
- Coverage parameters (glSampleCoverage, GL_SAMPLE_ALPHA_TO_COVERAGE,
  GL_SAMPLE_ALPHA_TO_ONE, GL_SAMPLE_COVERAGE, GL_SAMPLE_COVERAGE_VALUE,
  GL_SAMPLE_COVERAGE_INVERT).

Fixes piglit tests "EXT_framebuffer_multisample/accuracy" on
i965/Gen6.

v2:
- In intel_alloc_renderbuffer_storage(), quantize the requested number
  of samples to the next higher sample count supported by the
  hardware.  This ensures that a query of GL_SAMPLES will return the
  correct value.  It also ensures that MSAA is fully disabled on Gen7
  for now (since Gen7 MSAA support doesn't work yet).
- When reading from a non-MSAA surface, ensure that s_is_zero is true
  so that we won't try to read from a nonexistent sample.
intel: When AUB dumping, flush before emitting final bitmap command.

When we are generating an AUB dump, we make a final call to
aub_dump_bmp() as the context is being destroyed, to ensure that any
rendering performed before the application exits can be seen during a
simulation run.  However, we were doing this before flushing the batch
buffer; as a result simulation runs would not always see the effect of
all rendering commands.

This patch flushes the batch buffer just before making the final call
to aub_dump_bmp(), to ensure that all rendering is properly captured
in the final bitmap.
i965: Completely annotate the batch bo when aub dumping.

Previously, when the environment variable INTEL_DEBUG=aub was set,
mesa would simply instruct DRM to start dumping data to an .aub file,
but we would not provide DRM with any information about the format of
the data in various buffers.  As a result, a lot of the data in the
generate .aub file would be unannotated, making further data analysis
difficult.

This patch causes the entire contents of each batch buffer to be
annotated using the data in brw->state_batch_list (which was
previously used only to annotate the output of INTEL_DEBUG=bat).  This
includes data that was allocated by brw_state_batch, such as binding
tables, surface and sampler states, depth/stencil state, and so on.

The new annotation mechanism requires DRM version 2.4.34.

Reviewed-by: Eric Anholt <eric@anholt.net>
i965/msaa: Expand odd-sized MSAA surfaces to account for interleaving pattern.

Gen6 MSAA buffers (and Gen7 MSAA depth/stencil buffers) interleave
MSAA samples in a complex pattern that repeats every 2x2 pixel block.
Therefore, when allocating an MSAA buffer, we need to make sure to
allocate an integer number of 2x2 blocks; if we don't, then some of
the samples in the last row and column will be cut off.

Fixes piglit tests "EXT_framebuffer_multisample/unaligned-blit {2,4}
color msaa" on i965/Gen6.
i965/blorp: Generalize sampling code in preparation for Gen7

This patch generalizes the function
brw_blorp_blit_program::texture_lookup() so that it prepares the
arguments to the sampler message based on a caller-provided array
rather than assuming the argument order is always (u, v).

This paves the way for the messages we will need to use in Gen7, which
use argument orders (u, lod, v) and (si, u, v) (si=sample index).

It will also will allow us to read from arbitrary sample indices on
Gen6, by supplying the arguments (u, v, r, lod, si) to the SAMPLE_LD
message instead of just (u, v).
i965/blorp: Emit sample index in SAMPLE_LD message when necessary

This patch modifies the function brw_blorp_blit_program::texel_fetch()
to emit the SI (sample index) argument to the SAMPLE_LD message when
reading from a sample index other than zero.

Previously we were using the ugly hack of configuring multisampled
source surfaces as single-sampled, and accessing sample indices other
than zero by swizzling the texture coordinates in the WM program.
i965/blorp: Use MSDISPMODE_PERSAMPLE rendering when necessary

This patch modifies the "blorp" WM program so that it can be run in
MSDISPMODE_PERSAMPLE (which means that every single sample of a
multisampled render target is dispatched to the WM program, not just
every pixel).

Previously we were using the ugly hack of configuring multisampled
destination surfaces as single-sampled, and generating sample indices
other than zero by swizzling the pixel coordinates in the WM program.
i965/blorp: Factor gen6_blorp_emit_batch_head into separate functions.

This patch separates out the portions of gen6_blorp_emit_batch_head()
that emit 3DSTATE_MULTISAMPLE, 3DSTATE_SAMPLE_MASK, and
STATE_BASE_ADDRESS.  This paves the way for making the blorp code work
on Gen7, where additional command packets
(3DSTATE_PUSH_CONSTANT_ALLOC_VS and 3DSTATE_PUSH_CONSTANT_ALLOC_PS)
need to be emitted before 3DSTATE_MULTISAMPLE.
i965/blorp: Allocate space for push constants on Gen7.

On Gen7, push constants for shader programs are stored in the URB, so
blorp code needs to set aside space for them.  This was previously
unnecessary because blorp code was based on HiZ operations, which
don't require any shaders.

This patch adds a call from gen7_blorp_exec() to
gen7_allocate_push_constants(), to ensure that push constants are
assigned the correct location in the URB.  It also extracts a new
function gen7_emit_urb_state() from gen7_upload_urb(), which is
re-used by gen7_blorp_emit_urb_config() to ensure that the URB regions
used by all the pipeline stages leave room for the push constants.
i965/blorp: Use 16 pixel dispatch on Gen7 when there is a WM program.

When executing a blorp operation on Gen7 that does not need a WM
program (i.e. a HiZ operation), we use 32-pixel dispatch mode because
it's faster.  However, when executing a blorp operation that does need
a WM program, we need to use 16-pixel dispatch, because blorp WM
programs are compiled assuming 16-pixel dispatch.
i965/blorp: Implement proper texel fetch messages for Gen7.

On Gen6, texel fetch is always accomplished using the SAMPLE_LD
message, which accepts arguments (u, v, r, lod, si).  On Gen7, there
are two* texel fetch messages: SAMPLE_LD for non-MSAA surfaces, taking
arguments (u, lod, v), and SAMPLE_LD2DSS for MSAA surfaces, taking
arguments (si, u, v).

*Technically, there are other texel fetch messages, but they are used
for "compressed" MSAA surfaces, which we don't yet support.

This patch adds the proper message types and argument orderings for
Gen7.
i965/blorp: Enable blorp blits on Gen7.

Gen7 support for blorp (blits using the render bath) now works for
non-MSAA purposes.  This patch enables it.

Since blorp operations re-use the logic for HiZ ops, this required
adding a case to the switch statement in gen7_blorp_emit_wm_config(),
to allow for the case where no HiZ op is being performed.
i965/msaa: Add defines for Gen7.
i965/msaa: Properly handle sliced layout for Gen7.

Starting in Gen7, there are two possible layouts for MSAA surfaces:

- Interleaved, in which additional samples are accommodated by scaling
  up the width and height of the surface.  This is the only layout
  available in Gen6.  On Gen7 it is used for depth and stencil
  surfaces only.

- Sliced, in which the surface is stored as a 2D array, with array
  slice n containing all pixel data for sample n.  On Gen7 this layout
  is used for color surfaces.

The "Sliced" layout has an additional requirement: it must be used in
ARYSPC_LOD0 mode, which means that the surface doesn't leave any extra
room between array slices for miplevels other than 0.

This patch modifies the surface allocation functions to use the
correct layout when allocating MSAA surfaces in Gen7, and to set the
array offsets properly when using ARYSPC_LOD0 mode.  It also modifies
the code that populates SURFACE_STATE structures to ensure that
ARYSPC_LOD0 mode is selected in the appropriate circumstances.
i965/msaa: Validate Gen7 surface state constraints.

When a Gen7 SURFACE_STATE is configured for MSAA, a number of
additional constaints come in to play.  This patch adds a function
gen7_check_surface_setup() which verifies that all of those
constraints are met.
i965/msaa: Modify blorp code to account for Gen7 MSAA layouts.

Since blorp uses color textures and render targets to do all its work
(even when blitting stencil and depth data), it always has to
configure the Gen7 GPU to use the new "sliced" MSAA layout.  However,
when blitting stencil or depth data, the actual MSAA layout is
interleaved (as in Gen6).  Therefore, blorp has to do extra coordinate
transformation work to account for the interleaving manually.

This patch causes blorp to perform the necessary extra coordinate
transformations.

It also modifies the blorp SURFACE_STATE setup code for Gen7, so that
it does not try to correct the surface width and height to account for
MSAA, since "sliced" MSAA layout doesn't affect the surface width or
height.