msm: iommu-domains: Check IOMMU capability of device

Since, IOMMU will be enabled by default, check the IOMMU support
from hardware and decide the code path.

Change-Id: I1cea3ff145add2c8ed9e99edecebfb80b1c78760
Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
msm: Check for iommu with map_contiguous APIs

The msm_{un}map_contiguous_buffers lack checks for iommu_present.
This causes incorrect behavior if the APIs are used when IOMMU is
not present. Add these checks to do the correct action when IOMMU
is not present.

Change-Id: If358e17205cabdc97ed361ded4a954780df36f9c
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>

Conflicts:

	arch/arm/mach-msm/iommu_domains.c
ARM: idle: call idle notifiers before stopping nohz tick

If an idle notifier modifies a timer, calling the notifier after
the sched tick has been stopped may leave the sched tick set too
early.  Move teh idle notifier call before the call to
tick_nohz_stop_sched_tick.

Change-Id: I0db3284bec6d0193bc5e2a57650ab06bd8342319
Signed-off-by: Colin Cross <ccross@android.com>
msm: gic: Remove manual GIC programming for PPI trigger type

There is no need to manually program GIC for edge trigger PPIs
through board or device file hooks after the introduction of
enable_percpu_irq(.., type) interface. 2nd parameter of this
API needs to be used for programming the right trigger
type for the PPI.

Change-Id: Ie200928eb70fcbab6646ddd63acfd89a1a87f5fe
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
msm: bam_dmux: pin rx workqueue to core 0

Pin the receive workqueue so that it always runs on core 0.  Do this to
eliminate a race condition caused by the workqueue moving between cores in
the middle of a downlink data transfer.  If hit, the race condition will
cause the TCP/IP framework to process packets out of order for a short time
which could cause performance degradation due to unnecessary
retransmissions.

CRs-Fixed: 346788
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>

Conflicts:

	arch/arm/mach-msm/bam_dmux.c

Change-Id: I27831ecf4f6d0f55129f5490fe75ad5a7b46cf27
msm: bam_dmux: send powerdown ack to A2

When bam_dmux disconnects to the bam hardware in response to the A2
powering down, send an ack back to the A2 signaling that bam_dmux got
the powerdown signal and processed it.

This change optimizes the response time for back-to-back shutdown and
powerup sequences instead of requiring a hard coded delay in the A2 state
machine.

(cherry picked from commit 0b13a3522c4a68cb337398bb7bf66d3623d5f098)

Change-Id: I6e0d8036d189efba87873092562b8c5563c0db80
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
msm: bam_dmux: Disable BAM DMUX upon modem timeout

If the modem times out, disable BAM DMUX regardless of
the subsystem restart configuration.

If subsystem restart is disabled, log an extra message
since BAM DMUX will not be able to recover.

Signed-off-by: Eric Holmberg <eholmber@codeaurora.org>
(cherry picked from commit 90285e234912d8581a6dac40e8e5343bd35d5a8a)

Change-Id: Ic02329b4fb583740832c75f4534c2cfe0582185e
Signed-off-by: Ramakrishna Prasad N <crpn@codeaurora.org>

Conflicts:

	arch/arm/mach-msm/bam_dmux.c
msm: bam_dmux: fix downlink data race condition

As soon as downlink data buffers are queued to the bam hardware, they can
be used.  Not all of the steps necessary to enable complete processing
of downlink data are completed when buffers are first queued.  This
creates a race condition where bam_dmux could attempt to process data
before it is ready.  Move the buffer queuing process to later when data
processing requirements are met, thus eliminating the race condition.

CRs-Fixed: 338616
Change-Id: I61b1bac5b66cd178141080d04907e742c9d9f81a
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
(cherry picked from commit 2fb555e25e9e9f4facab1cd8a5f02edab7e93dd5)
msm: bam_dmux: fix duplicate dfab vote

If the A2 power collapse feature is disabled, bam_dmux will likely vote
for dfab twice in a row, which should not happen.  This is because the
first vote is done when it is assumed that A2 PC will be enabled, and that
vote is not accounted for in the internal driver state when A2 PC is
disabled.

CRs-Fixed: 361733
Change-Id: Ib3b1063dde5f3542b81d699b53d3e2cb35e40fa7
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
(cherry picked from commit 5f57ec970b0eff56c36bea196787c6aa6001993b)
msm: bam_dmux: Add locking around platform device calls

The channel state is used to determine if a platform device has been
registered on a particular channel.  In the case of a subsystem restart
while a channel is being opened, the subsystem restart can occur between
the channel state being set to opened and the platform device being
added.  This will result in the subsystem restart code seeing that the
channel is open and attempting to remove a platform device that has been
added.

This change adds mutex protection around the channel state updates and
the platform device add/remove calls to handle any race conditions.

CRs-fixed: 378060
Signed-off-by: Eric Holmberg <eholmber@codeaurora.org>
(cherry picked from commit a623da8bda62e95acf5991905af2847e8e326e09)

Change-Id: I8eef024141a2c81552439856aa9c77fc491354a3
Signed-off-by: Ramakrishna Prasad N <crpn@codeaurora.org>
msm: 8625: Disable Run Queue Statistics while running on single core.

This change disables Run Queue stats collection on single core targets.
Along with that this change also adds a new config option to make
RQS independent from SLEEP_STATS.

Change-Id: I27f5d7f35015378226215a40b961bbf059b8f502
Signed-off-by: Krishna Vanka <kvanka@codeaurora.org>
panic: Fix a possible deadlock in panic()

panic_lock is meant to ensure that panic processing takes
place only on one cpu; if any of the other cpus encounter
a panic, they will spin waiting to be shut down.

However, this causes a regression in this scenario:

1. Cpu 0 encounters a panic and acquires the panic_lock
   and proceeds with the panic processing.
2. There is an interrupt on cpu 0 that also encounters
   an error condition and invokes panic.
3. This second invocation fails to acquire the panic_lock
   and enters the infinite while loop in panic_smp_self_stop.

Thus all panic processing is stopped, and the cpu is stuck
for eternity in the while(1) inside panic_smp_self_stop.

To address this, disable local interrupts with
local_irq_disable before acquiring the panic_lock. This will
prevent interrupt handlers from executing during the panic
processing, thus avoiding this particular problem.

Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
(cherry picked from commit dd58afef43357f265e803c317bbaa91f8c440663)

Change-Id: I5f7ebcf2a028df265a57922b6c959e686a82026a
Signed-off-by: Swetha Basineni <sbasin@codeaurora.org>

Conflicts:

	kernel/panic.c
Perf: Dont reset PMU's if perf is not active

Perf would save and restore counters after resetting the PMU when
the CPU's came out of power collapse even if a perf session wasn't
active. Check if perf was running before going into power collapse
and only then reset PMU's while coming out.

This way PMU's can be accessed externally via the RPM or T32 without
perf intruding in counter output.

Change-Id: I33ac11b2a5cae21456341fde015aabe5b4bb8f52
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
arm: gic: Register irqdomain after adding it

Recently a change was added to break apart irq_domain_add() into
two functions. The first creates the domain, and the second
registers it.

This change abides to this new interface and registers the
GIC irq_domain after creating it.

Change-Id: I34c6a1f56dc27113a9b72f0fefa577276f91bbc8
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
arm: gic: Check for error code on irq_domain_add

This API now returns an error. Since gic_init_bases() is called
early on, there's probably not a whole lot we can do here except
send a warning.

Change-Id: I2835dacfa191db0ce70434de23e6ee540fe33b57
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
arm: gic: Configure the GIC to run in secure mode

Configure the GIC to run in secure mode and handle
secure as well as non-secure interrupts. This patch
adds an API to configure an IRQ as a secure IRQ so that
it can be treated as an FIQ in the secure mode.

Change-Id: Ic3321e76c95a4c10d6287ba418e84623e7004cb1
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
ARM: gic: Add support to access GIC in secure mode

Currently gic secure mode is enabled for all the v7 cpus.
For 8x25 we do not want to access GIC in secure mode as
we are observe issues of not able to clear the pending clear
registers when we come out of power collapse.

The Kconfig should make it flexible for targets who want to
support GIC in secure/non-secure modes.

Change-Id: Id7c85f5b741346233993966752607e5c4fb23e74
Signed-off-by: Taniya Das <tdas@codeaurora.org>
ARM: gic: Add spinlocks for SGIR/AIR/EOI for 8625

On 8625 due to bug in AHB MUX on hready, back to back write followed
by read (from any CPU) on QGIC2 registers (SGIR(WO) ,IAR(RO) and
write on EOI(WO)) cause the read data to get corrupted on AHB bus.

Due to this whenever a valid irq has occurs, and dispatched to the cpu
interface but still cpu reads the IAR as 0x0 and that particular IRQ
becomes active.
But due to incorrect irq id (read as 0x0), IRQ handler will not do
proper EOI for that particular interrupt and thus it gets trapped
in the active state.

Below is the qgic register dump from CPU-1, in this particular case
we see that SGI-3 is not getting clear as cpu reads this as 0x0.

AZSD:C0000200| 00240008 00000000 00008000 00000000 00000000 00000000
00000000 00000000 ..$.............................
AZSD:C0000280| 00240008 00000000 00008000 00000000 00000000 00000000
00000000 00000000 ..$.............................
AZSD:C0000300| 00040008 00000000 00000000 00000000 00000000 00000000
00000000 00000000 ................................
AZSD:C0000380| 00040008 00000000 00000000 00000000 00000000 00000000
00000000 00000000 ................................

As the interrupt gets trapped, no other interrupt received on the core is
services any more causing the system hang.

CRs-Fixed: 349219
Change-Id: Icad2c65114377a08984b1032566cfba811bb4ca8
Signed-off-by: Taniya Das <tdas@codeaurora.org>
ARM: gic: Move GIC based code out from mpm-8625

Moving code which modifies the GIC registers. As there is no global
lock in gic code, moving the code out.

Change-Id: I85a2bd580dbeefc942a3307f3c0cad8b1da509b7
Signed-off-by: Taniya Das <tdas@codeaurora.org>

Conflicts:

	arch/arm/mach-msm/mpm-8625.c
	arch/arm/mach-msm/platsmp-8625.c
ARM: gic: protect some of 8625 GIC functionality with irq spinlocks

msm_gic_spi_ppi_pending, msm_gic_save and core1_gic_configure_and_raise
gets called with interrupt enabled on the core0, so it is possible
that we get into the spinlock deadlock since interrupt like timer PPI
could get fired on core0 and get locked in gic_handle_irq() routine
itself, so move these spinlocks to irqsave variants to avoid this
scenario.

CRs-Fixed: 363249
Change-Id: I2d40d6e26f5d9dba4ee6b9d4602cd0e685226693
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>