ASoC: OMAP ABE: Update driver in order to probe with PM disable.

Update ABE driver in order to not fail when no OPP layer is
define for the AESS engine.

Signed-off-by: Sebastien Guiriec <s-guiriec@ti.com>
OMAPDSS: HDMI: Fix up build break for OMAP5 HDMI audio.

Put back HDMI device handle struct for audio API.

Signed-off-by: Sebastien Guiriec <s-guiriec@ti.com>
ASoC: OMAP: HDMI: Update driver for OMAP5 ES2.

Update driver for OMAP5 ES2.0 HW fix. Now all the rate can
be handled by HSDMI wrapper.

Signed-off-by: Sebastien Guiriec <s-guiriec@ti.com>
OMAPDSS: HDMI: Update HDMI audio rate according to ES2.0

OMAP5 ES 2.0 has updated HDMI wrapper that can support the CPUV
bits setting. Update HDMI core IP to reflect ES2.0 change.

Signed-off-by: Sebastien Guiriec <s-guiriec@ti.com>
OMAPDSS: DSS: Correct coding mistake in dss color format

Signed-off-by: Sreenidhi Koti <sreenidhi@ti.com>
Merge branch 'p-linux-omap-3.4' into p-android-omap-3.4

* p-linux-omap-3.4:
  OMAPDSS: DSS: Correct coding mistake in dss color format
  OMAPDSS: HDMI: Update HDMI audio rate according to ES2.0
  ASoC: OMAP: HDMI: Update driver for OMAP5 ES2.
  OMAPDSS: HDMI: Fix up build break for OMAP5 HDMI audio.
  ASoC: OMAP ABE: Update driver in order to probe with PM disable.

Conflicts:
	drivers/video/omap2/dss/hdmi.c

Change-Id: I5b2b3298a87dc5ae2c3fa033458cf968f80dec20
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
omap: bandgap: reorganize defines for register offsets

The bandgap register offsets and bit masks are already defined
in ctrl_module_core_54xx.h file. Modified the BG driver code
to use those offsets and bit masks.

Besides, this patch also prepares the code to better differentiate
between ES1.0 definitions and ES2.0 definitions. Idea is to
resolve the difference at ctrl_module_core_54xx.h. When the build
is for ES1.0, it will include the proper header. Users of this
header will not need to worry about which file to include.

This patch makes sure support for ES1.0 is kept in one piece.
Support for ES2.0 will be added later.

Change-Id: Ib8e3234dc3dd22ebb31a07d564f194b1e9a20d30
Signed-off-by: Radhesh Fadnis <radhesh.fadnis@ti.com>
omap: bandgap: introduce clock feature flag

The clock to Bandgap module is SW controlled on some version of
OMAP silicon (OMAP44xx and OMAP54xx ES1.0). But on OMAP54xx ES2.0
onwards this is HW-Auto controlled. Hence introduce a feature flag
to use/not-to-use SW enable/disable of BG clock.

Change-Id: Ic7634677a562b4a03f9d0754f3fc68cca4e8c36e
Signed-off-by: Radhesh Fadnis <radhesh.fadnis@ti.com>
omap5: bandgap: add ES2.0 changes

The bandgap module in OMAP5 ES2.0 has changed.

Following are the major changes:
1. Clock source has changed. The clock is sourced from L3_INSTR.
2. The Counter register has changed, there is no dedicated register.
Now it is part of mask register.
3. The ADC conversion/lookup table has changed.
4. New registers are added, Cumulative register and History buffer.

This patch makes sure that the driver code works on both ES1.0 and
ES2.0 with same functionality. This patch DOES-NOT address making use
of new features introduced (like Cumulative & History Buffer) in ES2.0.

Change-Id: Ibea3e04d18eedf0d9ed86fe1d6be4e6448aad3a8
Signed-off-by: Radhesh Fadnis <radhesh.fadnis@ti.com>
thermal: omap-bandgap: introduze FREEZE_BIT feature

For ES2.0 devices, it is not guaranteed that current DTEMP
or DTEMP0 from the history buffer are going to contain
correct values, due to desynchronization between BG clk
and OCP clk.

For this reason, this patch changes the driver to first:
a. consider a feature flag, FREEZE_BIT, in order to check
it is possible to freeze the history buffer or not.
b. whenever reading the temperature, it will fetch from
DTEMP1 instead of DTEMP or DTEMP0.

This WA is applicable only for OMAP5430 ES2.0.

Change-Id: Ie17613f3d12c3737faa33f5a7f959fbf0eff6875
Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
ARM: omap5: clockdomain: set iss clk domain to SWSUP

This patch sets the cam/iss clock domain from HW_AUTO to just
SW_SUP. This patch is based on a similar patch done for OMAP4,

"ARM: OMAP: clockdomain: set iss clk domain to just SWSUP"

This is done because CAM domain has no module wake-up dependency
with any other clock domain of the device and the dynamic
dependency from L3_main_2 is always disabled, the domain needs
to be in force wakeup in order to be able to be used or accessed
for configuration.

Also since there is no clock in the domain managed automatically
by the hardware, so there is no need to configure automatic
clock domain transition. SW should keep the SW_WKUP domain
transition as long as a module in the domain is required to
be functional.

Change-Id: Ibd82f0368fa030fefa2832bee4607a63405da7d3
Signed-off-by: Subramaniam C.A <subramaniam.ca@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tyler Luu <tluu@ti.com>
ARM: OMAP4: PRCM: Fix incorrect read of reset sources

The address of PRM_RSTST register and flag mask are incorrect,
so fix it.

Change-Id: I1277b6a1477c4a31ab3fbc0b12d1e270ffc3113f
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
ARM: OMAP5: PRCM: Add reset sources reading

There is not reset sources reading for OMAP5, so add it.

Change-Id: I02ed25a073f47c7699d75dea1eeb7f6b872b42e0
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
MFD: twl-core: Add ability to set one-time registers configuration

On some platforms, some the TWL registers may need to be configure once
during the initialization. Each time when we need to do that - struct
twl4030_platform_data and twl-core files need to be modified, because,
not all TWL registers/parameters are defined now in struct
twl4030_platform_data.

Hence, add common mechanism to set TWL one-time registers configuration
which will be applied at the end of TWL initialization. And to define
registers configuration in platform code as:
struct twl_reg_setup_array reg_setup_script = {
  {mod_no, addr, u8 val, desc;}     <- register 1
  {mod_no1, addr1, u8 val, desc1;}  <- register 2
  {0, 0, 0, NULL} <- terminator
}
and pass it to the twl-core through twl4030_platform_data.

Change-Id: Ia1b9ffa92dfe24b65c846d99aaaa9130f1e25671
Signed-off-by: Nishanth Menon <nm@ti.com>
[oleksandr.tyshchenko@ti.com: ported from K3.0]
Signed-off-by: Oleksandr Tyshchenko <oleksandr.tyshchenko@ti.com>
[grygorii.strashko@ti.com: made it common and move in TWL core]
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
ARM: OMAP4: TWL: ensure PREQ1 results in all active VCOREs to be down

Map VCORE1,2,3 appropriately to PREQ1 APP processor group so that
only APP processor can control it's power down status when OFF
mode is hit. Normally, OMAP sends a OFF voltage command to setup PMIC,
However, it is equally important to ensure that TWL will switch
off the relevant rail when the OFF voltage != 0.

Change-Id: I5d135d12e7a7c21254a4dc27a7974fa6a5dc3183
Signed-off-by: Nishanth Menon <nm@ti.com>
[oleksandr.tyshchenko@ti.com: ported from K3.0]
Signed-off-by: Oleksandr Tyshchenko <oleksandr.tyshchenko@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
ARM: OMAP4460: TWL: disable PD on VCORE1 shutdown

When the PREQ goes low, both VCORE1(VDD_CORE) and VDDD_MPU
start transitionning to 0 volt but VCORE1 discharge is faster
than VDD_MPU discharge. This causes reliability concern from
OMAP's perspective. So, we disable pull-down on VCORE1 to
slow down VDD_CORE discharge to make it comparable to VDD_MPU.

The Pull-down does not impact DVFS transition, and actual
OFF timing is not changed as well.

Change-Id: I36a737bafd43f3b2190320e55d9e326f16ef70a5
Signed-off-by: Nishanth Menon <nm@ti.com>
[oleksandr.tyshchenko@ti.com: ported from K3.0]
Signed-off-by: Oleksandr Tyshchenko <oleksandr.tyshchenko@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
ARM: OMAP4+: VC: Add function to control PMIC registers over SRI2C

Many simpler PMICs with a single I2C interface
still have configuration registers that may need
population. Typical being slew rate configurations
thermal shutdown configuration etc.
When these PMICs are hooked on I2C_SR, this function
allows these configuration registers to be accessed.

Change-Id: Iefc6acefdbb2305693cec802769b316533f68900
Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: Sergii Postulga <x0153364@ti.com>
ARM: OMAP4: TPS6236x: Add regulator initialization

Initialize TPS regulator during init,
setup slew rate and thermal shutdown.

Change-Id: I10d69725bdd199708033af5e02dd24a8b8f3d681
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: Sergii Postulga <x0153364@ti.com>
ARM: OMAP4460: SDP/TABLET: TWL: Remove binding to groups for VCORE3 and VMEM

This patch remove binding to groups for VCORE3 and VMEM
regulators in case of 4460.
In 4460 SOM VCORE3 and VMEM regulators are not used.
So, they should not be associated to any group.

Change-Id: Iab860041832fee41b28ce784a6af3244565b1266
Signed-off-by: Sergii Postulga <x0153364@ti.com>
Regulator: twl6030: setup regulator state for sleep state

TWL6030 enters into "sleep mode" when the PREQ lines are de-asserted.
This is the condition we enter when we are in APP processor suspend
state. However, TWL6030 regulator defaults for Sleep are set to
auto mode, to be certain that we consume lowest amount of power
by ensuring that the regulators and resources remain disabled when
we achieve sleep state in TWL6030 during suspend, we
explicitly setup the state as disabled for sleep when the regulator
is disabled and set as auto(default) when it is enabled. This
allows the current drivers which may use setmode in conjunction
with enable and disable to continue to get the benefit of the
auto mode.

Based on a patch by Baek.Kyung-Han <wildtaz.baek@samsung.com>

Change-Id: I464c45c87ae469bf0d8e44c6f9bd9e7f38d90a3e
Signed-off-by: Nishanth Menon <nm@ti.com>
[oleksandr.tyshchenko@ti.com: ported from K3.0]
Signed-off-by: Oleksandr Tyshchenko <oleksandr.tyshchenko@ti.com>