spi_qsd: Add support for new QUPe controller.

The SPI driver is modified to support the new QUPe
controller (version 0x2). The SPI functionality of the
controller is very similar to the previous QUPe
controller (version 0x1). This change addresses
some cleanup along with register address modifications and
flow changes.

Change-Id: I15e7084dd54a1144bd85bf75efd7757b545d24f9
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
msm: v4l2: fix support for test app.

This commit fixes bug in query-cap ioctl and
adds ION support for case where buffers are
allocated in the kernel with mmap. This change
is required to fix the V4L2 command line test app.

Change-Id: I50a535e8a0af60ff7d86341a3f726ed81a630fb0
Signed-off-by: Ankit Premrajka <ankitp@codeaurora.org>
msm: v4l2: add ISP support for more formats.

This change adds support for YUV422_NV61 and YUV422_NV16
formats in the V4L2 driver.

Change-Id: I99f8604d07a7b8290b4eb82d8c21f88db9c7f60f
Signed-off-by: Ankit Premrajka <ankitp@codeaurora.org>
msm: pm-8x60: Check for SPM status to verify CPU_DEAD

On newer MSM targets including 8960, the clocks for the cpu being
hot unplugged is turned off during the CPU_DEAD callback on the
cpu initiating the hotplug. The initiating CPU polls for the SPM sleep
status of the secondary cpu in platform_cpu_kill to ensure that the
secondary cpu has been power collapsed before returning to process the
CPU_DEAD callbacks.

Change-Id: I5085c353f1b5d08622504cea8430bb8bdb1192f6
Signed-off-by: Maheshkumar Sivasubramanian <msivasub@codeaurora.org>
msm: clock-8960: Remove QDSS clock support

These clocks are now managed by the RPM via a QDSS resource (not
the RPM clock driver) and thus no longer need to be controlled by
Linux. Remove support for these clocks.

Change-Id: I1df9c16920c4df0947b16fdd3595cdbf4659d0b0
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
input: atmel_mxt_ts: Release irq and reset gpios

Cleanup and release the gpio pins for irq and reset
when the module is removed.

Change-Id: Id264411a786c7490506271bef2d6f7e55e7d07fb
Signed-off-by: Mohan Pallaka <mpallaka@codeaurora.org>
tracing: Clean up tb_fmt to not give faulty compile warning

gcc incorrectly states that the variable "fmt" is uninitialized when
CC_OPITMIZE_FOR_SIZE is set.

Instead of just blindly setting fmt to NULL, the code is cleaned up
a little to be a bit easier for humans to follow, as well as gcc
to know the variables are initialized.

Change-Id: Ia5fb9cc6be8eadae9af3a5636a2459ed7cd48662
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
irq: irqdomain: Add support for dynamic irq_desc allocations

The current irq_domain_add() design assumes the underlying
irq_descs are valid when irq_domain_add() is called. It also
assumes that every hwirq enlisted in the irq_domain is valid.
Often, these assumptions are not correct.

Typically, irq_domain_add() is called at board_init time, but
sometimes interrupt chip drivers are not initialized until an
underlying bus is probed. When using SPARSE_IRQ, it's quite
natural to hold off allocating irq_descs until the board
topology specifies them as included.

And in such device topologies, there's no guarantee that chip
interrupt numbers will be contiguous. For example, each hwirq may
map to a particular device, but that device may or may not be
present in the actual hardware configuration. In order to support
this, we need the concept of an irq_domain that supports holes
in it.

In order to solve these problems, let's break the irq_domain
creation from the irq registration process. The irq_domain
creation can occur at init time and then have no dependencies. An
interrupt is not 'registered' with the domain until its resources
have already been allocated by the chip driver. For simple cases,
an additional API is provided to register the entire
logical irq_domain range to provide feature parity with what
already exists.

Change-Id: Ie3340d07ba8663196dc87d1185e3bb7fbed4be4d
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
arm: gic: Register irqdomain after adding it

Recently a change was added to break apart irq_domain_add() into
two functions. The first creates the domain, and the second
registers it.

This change abides to this new interface and registers the
GIC irq_domain after creating it.

Change-Id: I34c6a1f56dc27113a9b72f0fefa577276f91bbc8
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
irq: irqdomain: Change irq_domain_add to detect errors

It should not be valid to add an irq_domain with a logical irq
range that overlaps with another already registered to the
system. Return an error on such an occurrence.

This change also inherently sorts the irq_domains by logical
irq_base as they are added.

Change-Id: Idef697dbe4584d783703d053fbf09f1b17e62ab0
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
arm: gic: Check for error code on irq_domain_add

This API now returns an error. Since gic_init_bases() is called
early on, there's probably not a whole lot we can do here except
send a warning.

Change-Id: I2835dacfa191db0ce70434de23e6ee540fe33b57
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
irq: irqdomain: Add API to find free irq range

When registering irq chip drivers, one common requirement is to
specify the irq_domain irq_base and nr_irq. These fields represent
the system wide logical interrupt range the domain occupies.
For systems with only one interrupt controller, it's trivial to
know these values. But for systems with several irq chip drivers,
it becomes painful to keep track of interrupt ranges in platform
defines. These create needless compile time dependencies, of
which the Device Tree aims to solve.

irq_alloc_desc() can search for a free irq, but is very
inefficient for determining the availability of large ranges.
Additionally, some irq chip drivers allocate irq descriptors
lazily. For example, portions of the Device Tree may not be parsed
until a particular bus is probed. But of_irq_init() is intended to
be run at init time, and this is a natural time to allocate irq
domains. Thus by the time we allocate our irq descriptors, we already
need to know a range of acceptable irqs to use for the domain.

To solve these problems, let's introduce
irq_domain_find_free_range(), which will return to the caller the
first available irq domain range not used already by the system.
This range can then be specified with irq_domain_add().

Change-Id: I8b0f5d25b173c76b8fc5d4f46b3fe9c6bf5c3c8f
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
Merge "input: atmel_mxt_ts: Release irq and reset gpios" into msm-3.0
Merge "msm: clock-8960: Remove QDSS clock support" into msm-3.0
Merge "msm: pm-8x60: Check for SPM status to verify CPU_DEAD" into msm-3.0
Merge "tracing: Clean up tb_fmt to not give faulty compile warning" into msm-3.0
Merge changes I8b0f5d25,I2835dacf,Idef697db,I34c6a1f5,Ie3340d07 into msm-3.0

* changes:
  irq: irqdomain: Add API to find free irq range
  arm: gic: Check for error code on irq_domain_add
  irq: irqdomain: Change irq_domain_add to detect errors
  arm: gic: Register irqdomain after adding it
  irq: irqdomain: Add support for dynamic irq_desc allocations
Merge "spi_qsd: Add support for new QUPe controller." into msm-3.0
Merge changes I99f8604d,I50a535e8 into msm-3.0

* changes:
  msm: v4l2: add ISP support for more formats.
  msm: v4l2: fix support for test app.
drivers: android: Add android binder proc entries.

This is from marvel-gb-mr-2.6.35-a66971c.