This patch is needed to make c++ exceptions work for mips16.

Mips16 is really a processor decoding mode (ala thumb 1) and in the same
program, mips16 and mips32 functions can exist and can call each other.

If a jal type instruction encounters an address with the lower bit set, then
the processor switches to mips16 mode (if it is not already in it). If the
lower bit is not set, then it switches to mips32 mode.

The linker knows which functions are mips16 and which are mips32.
When relocation is performed on code labels, this lower order bit is
set if the code label is a mips16 code label.

In general this works just fine, however when creating exception handling
tables and dwarf, there are cases where you don't want this lower order
bit added in.

This has been traditionally distinguished in gas assembly source by using a
different syntax for the label.

lab1:      ; this will cause the lower order bit to be added
lab2=.     ; this will not cause the lower order bit to be added

In some cases, it does not matter because in dwarf and debug tables
the difference of two labels is used and in that case the lower order
bits subtract each other out.

To fix this, I have added to mcstreamer the notion of a debuglabel.
The default is for label and debug label to be the same. So calling
EmitLabel and EmitDebugLabel produce the same result.

For various reasons, there is only one set of labels that needs to be
modified for the mips exceptions to work. These are the "$eh_func_beginXXX" 
labels.

Mips overrides the debug label suffix from ":" to "=." .

This initial patch fixes exceptions. More changes most likely
will be needed to DwarfCFException to make all of this work
for actual debugging. These changes will be to emit debug labels in some
places where a simple label is emitted now.

Some historical discussion on this from gcc can be found at:
http://gcc.gnu.org/ml/gcc-patches/2008-08/msg00623.html
http://gcc.gnu.org/ml/gcc-patches/2008-11/msg01273.html 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170279 91177308-0d34-0410-b5e6-96231b3b80d8
MCPureStreamer.cpp: Try to fix build, pruning EmitDebugLabel().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170280 91177308-0d34-0410-b5e6-96231b3b80d8
Declare class DwarfDebug before use instead of relying on a forward declaration
from some other unrelated header.

Patch by Kai.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170284 91177308-0d34-0410-b5e6-96231b3b80d8
Replace ${:comment} with the comment symbol.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170286 91177308-0d34-0410-b5e6-96231b3b80d8
Change XCoreAsmPrinter to lower MachineInstrs to MCInsts before emission.

This change adds XCoreMCInstLower to do the lowering to MCInst and
XCoreInstPrinter to print the MCInsts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170288 91177308-0d34-0410-b5e6-96231b3b80d8
Set instruction size correctly in XCoreInstrFormats.td

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170289 91177308-0d34-0410-b5e6-96231b3b80d8
Mark anything deriving from PseudoInstXCore as a pseudo instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170290 91177308-0d34-0410-b5e6-96231b3b80d8
Remove invalid instruction encodings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170291 91177308-0d34-0410-b5e6-96231b3b80d8
Add XCore disassembler.

Currently there is no instruction encoding info and
XCoreDisassembler::getInstruction() always returns Fail. I intend to add
instruction encodings and tests in follow on commits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170292 91177308-0d34-0410-b5e6-96231b3b80d8
Add instruction encodings and disassembly for 1r instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170293 91177308-0d34-0410-b5e6-96231b3b80d8
Add tests for disassembly of 1r XCore instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170295 91177308-0d34-0410-b5e6-96231b3b80d8
Add debug prints for when optimizeLoadInstr folds a load.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170298 91177308-0d34-0410-b5e6-96231b3b80d8
Lift the integer splat computation into a helper function.

No functionality changed. Refactoring leading up to the fix for PR14478
which requires some significant changes to the memset and memcpy
rewriting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170299 91177308-0d34-0410-b5e6-96231b3b80d8
Extract the logic for inserting a subvector into a vector alloca.

No functionality changed. Another step of refactoring toward solving
PR14487.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170300 91177308-0d34-0410-b5e6-96231b3b80d8
Fix the first part of PR14478: memset now works.

PR14478 highlights a serious problem in SROA that simply wasn't being
exercised due to a lack of vector input code mixed with C-library
function calls. Part of SROA was written carefully to handle subvector
accesses via memset and memcpy, but the rewriter never grew support for
this. Fixing it required refactoring the subvector access code in other
parts of SROA so it could be shared, and then fixing the splat formation
logic and using subvector insertion (this patch).

The PR isn't quite fixed yet, as memcpy is still broken in the same way.
I'm starting on that series of patches now.

Hopefully this will be enough to bring the bullet benchmark back to life
with the bb-vectorizer enabled, but that may require fixing memcpy as
well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170301 91177308-0d34-0410-b5e6-96231b3b80d8
Remove store forms of DEC/INC from isDefConvertible. Since they are stores they don't have a register def.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170303 91177308-0d34-0410-b5e6-96231b3b80d8
Add rest of BMI/BMI2 instructions to the folding tables as well as popcnt and lzcnt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170304 91177308-0d34-0410-b5e6-96231b3b80d8
Simplify BMI ANDN matching to use patterns instead of a DAG combine. Also add ANDN to isDefConvertible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170305 91177308-0d34-0410-b5e6-96231b3b80d8
Remove EFLAGS from the BLSI/BLSMSK/BLSR patterns. The nodes created by DAG combine don't contain an EFLAGS def.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170308 91177308-0d34-0410-b5e6-96231b3b80d8
Fix comment typo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170317 91177308-0d34-0410-b5e6-96231b3b80d8