m68k/aasmcpu, taicpu.spilling_get_operation_type: add support for A_SUBX

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22724 3ad0048d-3df7-0310-abae-a5850022a9f2
m68k/ra68kmot.pas, tm68kmotreader.Assemble:
  the asmr_d_*_reading messages need an argument which specifies in which style the assembler code
  is read; this is most importantly used on i386; on m68k we currently don't have multiple styles,
  so simply disable these messages

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22725 3ad0048d-3df7-0310-abae-a5850022a9f2
m68k/cgcpu.pas, tcg68k: implement a_jmp_name

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22726 3ad0048d-3df7-0310-abae-a5850022a9f2
rtl/m68k/sysnr.inc:
  adjust syscalls just enough so that we don't have any duplicate symbols; the correctness will
  be verified once we have linkable code

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22727 3ad0048d-3df7-0310-abae-a5850022a9f2
m68k/n68kcnv.pas, tm68ktypeconvnode.second_int_to_bool:
  implement case "LOC_JUMP" (with a more or less blindly copy from
  x86/nx86cnv.pas, tx86typeconvnode.second.int_to_bool; this now allows that the system unit can
  be compiled, but not yet assembled

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22728 3ad0048d-3df7-0310-abae-a5850022a9f2
rtl/m68k: Added mathu(h).inc with dummy implementations of SetExceptionMask and GetExceptionMask

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22729 3ad0048d-3df7-0310-abae-a5850022a9f2
aggas.pas: m68k-linux needs preceding ".section" as well

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22730 3ad0048d-3df7-0310-abae-a5850022a9f2
m68k/n68kcnv.pas, tm68ktypeconvnode.second_int_to_bool:
* remove comments regarding needed LOC_JUMP implementation
* don't call flags2reg if the location is LOC_JUMP as there isn't a register to set the flags to
  (this allows fpc_mul_qword and fpc_mul_int64 to be assembled)

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22731 3ad0048d-3df7-0310-abae-a5850022a9f2
m68k/cgcpu.pas, tcg68k.a_op_const_reg:
  * use andi/ori for constant values
  * use a scratch register if target is an address register (there seems to exist an omnious
    anda/ora instruction though, but GNU as doesn't seem to handle it... maybe I haven't set
    the CPU type correctly, so I'll need to investigate this so we can hopefully remove the
    need for a scratch register for certain CPU types ;) )

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22732 3ad0048d-3df7-0310-abae-a5850022a9f2
m68k/cgcpu.pas, tcg68k.a_op_const_reg:
  leave "and" and "or" as "and" and "or" as according to the assembly language reference the
  assembler should automatically choose the correct instruction (though Coldfire still should
  be tested for ORI/ANDI to CCR

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22733 3ad0048d-3df7-0310-abae-a5850022a9f2
m68k/ag68kgas.pas, getreferencestring:
  It seems that GNU as needs the syntax "offset(register.size*scale)" if the base address
  register is ommited instead of "offset(,register.size*scale)". Now the System unit
  assembles and nearly the complete RTL can be built.

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22734 3ad0048d-3df7-0310-abae-a5850022a9f2
rtl/linux/m68k/prt0.as:
  Add __stkptr variable

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22735 3ad0048d-3df7-0310-abae-a5850022a9f2
m68k/cgcpu.pas, tcg68k.g_proc_exit:
* generate special return code for non-68020 CPU which don't support RTD instruction (based on
  out code a few lines further down)

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22736 3ad0048d-3df7-0310-abae-a5850022a9f2
assemble.pas, texternalcompiler.makecmdline:
* pass the correct architecture to the assembler (later we might switch to a $ARCH approach...)

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22737 3ad0048d-3df7-0310-abae-a5850022a9f2
Fixed reference handling mostly for Coldfire CPUs. While they are conceptually based on
M68000 CPUs they are nevertheless more restricted in some cases, so these need to be
handled explicitely (especially if symbols are involved).

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22738 3ad0048d-3df7-0310-abae-a5850022a9f2
For now completely disable (I)MUL/(I)DIV support for Coldfire and pass through the RTL routines
(of which the names had changed from FPC_MUL_LONGWORD->FPC_MUL_DWORD and FPC_MOD_CARDINAL->
FPC_MOD_DWORD).
Also disable the usage of FPU opcodes for Coldfire.

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22739 3ad0048d-3df7-0310-abae-a5850022a9f2
Replace DBRA instruction for Coldfire with a SUB/BRA combination in the for-loop-code-
generation and the assembly helpers in the RTL as DBRA is not supported by Coldfire.

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22740 3ad0048d-3df7-0310-abae-a5850022a9f2
Use the correct frame pointer register: A6 on Unixes and A5 on everything else. The only
open question is embedded systems (currently it counts as "everything else").

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22741 3ad0048d-3df7-0310-abae-a5850022a9f2
m68k also uses a non fixed stack with an equivalent to PUSH/POP so don't reorder parameters
if the required stack offset tells otherwise.

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22742 3ad0048d-3df7-0310-abae-a5850022a9f2
Various adjustments to the RTL for m68k:
* enable the 6 parameter syscall variant (still everything dummied out though)
* add termios constants
* don't change signal handlers for now
* disable assembly set routines as set handling was changed

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22743 3ad0048d-3df7-0310-abae-a5850022a9f2