ARM: LPC32xx: Add NAND flash timing to PHY3250 board dts

This patch adds necessary NAND flash timings to the board specific dts file of
the PHY3250 reference board of the LPC32xx SoC.

Signed-off-by: Roland Stigge <stigge@antcom.de>
Tested-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
ARM: LPC32xx: Clock initialization for NAND controllers

This patch adds clock initialization for the MLC NAND controller of the LPC32xx
SoC and adjusts it for the SLC controller.

Signed-off-by: Roland Stigge <stigge@antcom.de>
ARM: LPC32xx: Remove SLC controller initialization from platform init

Since we now support two MTD NAND controllers (MLC and SLC) for LPC32xx via DT,
we don't initialize the SLC controller statically anymore, but do it via the
clock setup (see previous patch).

Signed-off-by: Roland Stigge <stigge@antcom.de>
Tested-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
ARM: LPC32xx: Add DMA configuration to platform data

This patch adds DMA channel configuration to the LPC32xx platform file.  The
configured DMA signalling is generic for LPC32xx SoC and is not board specific.

Signed-off-by: Roland Stigge <stigge@antcom.de>
ARM: LPC32xx: Adjust dtsi file for MLC controller configuration

This patch takes into account that the MTD NAND MLC controller needs more
registers, located actually before the previously allocated memory range,
already starting at 200a8000 instead of 200b0000.

Further, the interrupt for the controller is configured.

Signed-off-by: Roland Stigge <stigge@antcom.de>
Tested-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
ARM: LPC32xx: Add dts for EA3250 reference board

There is another reference/development board for the LPC32xx SoC (besides the
Phytec 3250): The Embedded Artists LPC3250 board. This patch adds a default dts
file for it.

Signed-off-by: Roland Stigge <stigge@antcom.de>
Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
ARM: LPC32xx: DTS adjustment for key matrix controller

This patch connects the lpc32xx-key driver to the LPC32xx platform (via
lpc32xx.dtsi), and more specifically to the reference board via its dts file.

Signed-off-by: Roland Stigge <stigge@antcom.de>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
ARM: LPC32xx: Clock adjustment for key matrix controller

The clock.c file needs to be changed to match the automatic device name to its
clock.

Signed-off-by: Roland Stigge <stigge@antcom.de>
Acked-by: Rob Herring <rob.herring@calxeda.com>
ARM: LPC32xx: Defconfig update

This defconfig update for the LPC32xx SoC platform adds the new drivers in v3.5
and drivers typically used in systems with the LPC32xx chip.

Signed-off-by: Roland Stigge <stigge@antcom.de>
Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
ARM: LPC32xx: Add MMC controller support

This patch adds support for the MMC controller of the LPC32xx SoC to the
platform initialization via the pl08x primecell driver. Lacking more complete
DT support, done via DT auxdata.

Signed-off-by: Roland Stigge <stigge@antcom.de>
Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
ARM: LPC32xx: DTS adjustment for using pl18x primecell

This patch adjusts the dts files to reference the pl18x primecell driver
correctly.

Signed-off-by: Roland Stigge <stigge@antcom.de>
ARM: LPC32xx: DT conversion of Standard UARTs

This patch switches from static serial driver initialization to devicetree
configuration. This way, the Standard UARTs of the LPC32xx SoC can be enabled
individually via DT.

E.g., instead of Kconfig configuration, the phy3250.dts activates
UARTs 3 and 5.

Signed-off-by: Roland Stigge <stigge@antcom.de>
Tested-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
ARM: LPC32xx: High Speed UART configuration via DT

This patch fixes the DTS files for the High Speed UARTs 1, 2 and 7 of the
LPC32xx SoC, adjusting the compatible strings, adding interrupts and status
configuration. On the PHY3250 reference board, UART2 is enabled.

Signed-off-by: Roland Stigge <stigge@antcom.de>
Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
ARM: LPC32xx: Remove mach specific ARCH_NR_GPIOS, use default

ARCH_NR_GPIOS was defined statically to include exactly all SoC specific GPIOs.
Now if additional GPIOs need to be added dynamically, e.g. via DT, none are
available. Removing the mach specific setting, leaving ARCH_NR_GPIOS to the
default of 256 (currently in include/asm-generic/gpio.h).

Signed-off-by: Roland Stigge <stigge@antcom.de>
Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
ARM: LPC32xx: Fix lpc32xx.dtsi status property: "disable" -> "disabled"

This patches fixes some status = "disable" strings to "disabled", the correct
way of disabling nodes in the devicetree.

Signed-off-by: Roland Stigge <stigge@antcom.de>
ARM: LPC32XX: Build arch dtbs

Add ea3250.dtb and phy3250.dtb to the list of dtbs to be built

Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: Roland Stigge <stigge@antcom.de>
ARM: LPC32XX: Add dt settings to the at25 node

Add the reg, cs-gpios and max-frequencies that are needed for spi
device registry in phy3250.
Adds also the pl022 internal transfers details via dt

Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
ARM: LPC32XX: remove spi chipselect request from board init

The lpc32xx spi0 chipselect will be requested directly from the
pl022 driver

Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
ARM: LPC32XX: remove spi chip definitions

Leave chipselect and spi devices binding to the devicetree

Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
ARM: LPC32XX: cleanup board init, remove duplicate clock init

Remove SSP0, CLCD and DMA clocks that are already migrated to
the clock framework.

Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>