temp control: setting templimit to 0 will revert to kernel default
checkv: show current iva and core frequencies and voltages
cpufreq: interactive: fixup trace of string params

Change-Id: Iac47f62437e61b13724afbbf9df1a0729f58f236
Signed-off-by: Todd Poynor <toddpoynor@google.com>
OPP: give 1.65ghz a unique fuse offset
OMAP4: IRQ: Fix OMAP44XX_IRQ_CPUIDLE_POKE0 definition

According to OMAP4470 TRM the MA_IRQ_60 is busy for
L3_STAT_ALARM_IRQ L3 NoC statistics collector alarm interrupt.

The MA_IRQ_106 is reserved in all OMAP4 chips, so it's selected
for using as OMAP44XX_IRQ_CPUIDLE_POKE0.

Change-Id: Iba7f727035c71db009defe684a66fb8c58ee3f93
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Revert "ARM: SMP: use a timing out completion for cpu hotplug"

This reverts commit 7d14831baa1409e403b714d6e48d35370868acb1.

suspected of reboot issues - revert for now
v3.6.0exp2-230
OMAP4: DVFS: Fix scaling dependent frequencies.

When scaling dependent frequencies down it is observed that the order
in which frequencies are changed is incorrect.  For example, when core
domain changes OPP down from OPP119 to OPP50 the order is:
a) scale L3 freq down to OPP50
b) scale SGX freq down to OPP50
which is wrong.

Frequencies are scaled in order devices are registered in omap dvfs
framework in device list. Devices are inserted to the list in order,
such as dependences are satisfied if scaling frequencies up.

When scaling frequencies down traverse list backwards.

This patch is related to defect OMAPS00268574 "OMAP4xxx: DVFS down
scale issue with L3 clock.

Change-Id: I752bcb264cac12514f358986a906f29ee81ba75e
Signed-off-by: Oleksandr Kozaruk <oleksandr.kozaruk@ti.com>

Patch Set 3
Revert "OMAP4: DSS: Implement workaround for Errata ID:i733."

This reverts commit c9272c2d7898c54a7d26e04a28dc08f47cd15343.
OMAP4: DSS: Implement workaround for Errata ID:i733.

Description of Errata i733:
Due to wrong timings, all register accesses transitioning through the L4
interconnect toward DSS are not reliable.

Workaround:
DSS register access should be addressed through the L3 interconnect.

This change fixes errata by using L3 for access to DSS in dss_hwmod
instead of L4.

Silicon Versions Impacted:
OMAP4430 ES1.0, ES2.0, ES2.1, ES2.2, ES2.3
OMAP4460 ES1.0, ES1.1
OMAP4470 ES1.0

Change-Id: Ie087b861ee653a3beeacba74c3afe7b1a0490ed4
Co-author: Raghuveer Murthy <raghuveer.murthy@ti.com>
Signed-off-by: Mykhailo Denysiuk <x0172934@ti.com>
OMAPDSS: drop small YUV encoded frames on OMAP44xx

OMAP44xx has hardware limitation: in stall mode, when the frame pixel size
is less than output SyncFifo depth(16), DISPC hangs without sending any data.
Simple workaround is to drop such frame, as cases when YUV frames of this size
are very rare.

Change-Id: I31dc262b07a52b66209c093f136ad2bac66f9439
Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>

Patch Set 1
Revert "OMAP4: MUSB: peripheral isoch IN endpt support"

This reverts commit c4f4d53fc613f69ea88e87643795c6323729ca96.

Breaks USB tether
Custom SR Tuning V2: allow SR to calibrate high voltages

For MPU only, should have zero effect on IVA and CORE

(for my experimental builds, since stable doesn't need it)
net: wireless: bcmdhd: Fix division by 0 if dhd_watchdog_ms is 0

Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
usb: musb: implement (un)map_urb_for_dma hooks

MUSB controller cannot work in DMA mode with misaligned buffers,
switching in PIO mode.

HCD core has hooks that allow to override the default DMA
mapping and unmapping routines for host controllers that have
special DMA requirements, such as alignment contraints.

It is observed that work in PIO mode is slow and it's better
to align buffers properly before pass them to MUSB

Some ideas taken from ehci-tegra.c

Change-Id: Id6eeaa811063d408f121c79012aba921f26eb582
Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>

Patch Set 1
usb: hcd: Add a dma_align flag

Some host controllers has special DMA requirements,
such as alignment contraints.
Added a flag dma_align for indicating this requirement

Change-Id: I06277ade030429a832e6db38cc695128a1033f08
Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>

Patch Set 1
usb: musb: indicate DMA alignement requirement

The MUSB host controller requires DMA buffers to be aligned.
If DMA buffers are misaligned it will use (un)map_urb_for_dma
for re-aligning buffers.
This often happens with USB network adapters, where skbuff
alignement is often in the middle of a 4-byte dword.
Indicate host controller DMA alignement requirement for such cases

Change-Id: I8a03f392caff762e9b48b65d31a119fdd833ae69
Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>

Patch Set 2
Increase wi-fi voltage by 0.25mV for stability purposes.
checkt: show SR VMIN
sr script: "sr high" to enable/disable high voltage smartreflex

(also some additional error checking)
Does not persist at boot yet - it's a dangerous option.