ARM: KVM: Only kick a vcpu if it is actually in guest mode

Check that a vcpu is actually running before kicking it.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
ARM: KVM: Keep track of currently running vcpus

When an interrupt occurs for the guest, it is sometimes necessary
to find out which vcpu was running at that point.

Keep track of which vcpu is being tun in kvm_arch_vcpu_ioctl_run(),
and allow the data to be retrived using either:
- kvm_arm_get_running_vcpu(): returns the vcpu running at this point
  on the current CPU. Can only be used in a non-preemptable context.
- kvm_arm_get_running_vcpus(): returns the per-CPU variable holding
  the the running vcpus, useable for per-CPU interrupts.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
ARM: KVM: Initial VGIC infrastructure support

Wire the basic framework code for VGIC support. Nothing to enable
yet.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
ARM: KVM: Initial VGIC MMIO support code

Wire the initial in-kernel MMIO support code for the VGIC, used
for the distributor emulation.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
ARM: KVM: VGIC distributor handling

Add the GIC distributor emulation code. A number of the GIC features
are simply ignored as they are not required to boot a Linux guest.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
ARM: KVM: VGIC virtual CPU interface management

Add VGIC virtual CPU interface code, picking pending interrupts
from the distributor and stashing them in the VGIC control interface
list registers.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
ARM: KVM: VGIC interrupt injection

Plug the interrupt injection code. Interrupts can now be generated
from user space.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
ARM: KVM: VGIC control interface world switch

Enable the VGIC control interface to be save-restored on world switch.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
ARM: KVM: VGIC initialisation code

Add the init code for the hypervisor, the virtual machine, and
the virtual CPUs.

An interrupt handler is also wired to allow the VGIC maintainance
interrupts, used to deal with level triggered interrupts and LR
underflows.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
ARM: KVM: vgic: reduce the number of vcpu kick

If we have level interrupts already programmed to fire on a vcpu,
there is no reason to kick it after injecting a new interrupt,
as we're guaranteed that we'll exit when the level interrupt will
be EOId (VGIC_LR_EOI is set).

The exit will force a reload of the VGIC, injecting the new interrupts.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
ARM: KVM: Add VGIC configuration option

It is now possible to select the VGIC configuration option.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
ARM: KVM: VGIC: Update KVM API documentation

Reflect the changes in the API due to the introduction of VGIC.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
KVM: ARM: __kvm_va_to_pa()

Create a helper to do the guest va->pa mapping.  Then take the code out of the
exit path, and use normal C.

copy_from_guest_va() is a bit more generic than it needs to be, but
not much.

Signed-off-by: Rusty Russell <rusty.russell@linaro.org>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
KVM: ARM: Let guest instruction mapping fail.

There is a race (SMP guest and host only) where the instruction we
faulted on is unmapped before we get to reading it.  In this (very
unlikely!) case, we should simply return to the guest.  It will
probably do the right thing next time.

Signed-off-by: Rusty Russell <rusty.russell@linaro.org>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
KVM: ARM: Atomically read guest instruction,

Ben Herrenschmidt pointed out a nasty race:
(1) Guest complicated mmio instruction traps.
(2) The hardware doesn't tell us enough, so we need to read the actual
    instruction which was being exectuted.
(3) KVM maps the instruction virtual address to a physical address.
(4) The guest (SMP) swaps out that page, and fills it with something else.
(5) We read the physical address, but now that's the wrong thing.

This is so rare that we can stop all the vcpus from running when it
happens (if no VCPUS are running, this just means getting and
releasing a spinlock).

Signed-off-by: Rusty Russell <rusty.russell@linaro.org>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
KVM: ARM: 16-bit Thumb instructions shouldn't generate error

When copying guest instructions on an 'invalid' IO abort, we don't want
to just greedily copy 32 bits, as a 16-bit thumb instruction at the end
of a page may exist such that the following page is not mapped in the
guest and our attempt to translate the VA->IPA of that page will just
continously fail.  No, instead we do this madness twice, checking the
length of the instruciton in between.

Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
KVM: ARM: Inject data/prefetch aborts in guest

Inject these aborts if the guest tries to do something really weird.
It's nicer to tell the guest that there was an abort than just
forcefully kill the whole thing.

For now we always tell the guest it was a debug generated abort, but we
can make this scheme more flexible in the future.

Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
KVM: ARM: Cleanup and fix load/store instruction decoding

Split the kvm_emulate_mmio_ls into a separate decoding function
and also supports emulated mmio writes now.

Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
KVM: ARM: Support Thumb MMIO instruction decoding

We only support instruction decoding for valid reasonable MMIO operations
where trapping them do not provide sufficient information in the HSR (no
16-bit Thumb instructions provide register writeback that we care about).

The following instruciton types are NOT supported for MMIO operations
despite the HSR not containing decode info:
 - any Load/Store multiple
 - any load/store exclusive
 - any load/store dual
 - anything with the PC as the dest register

Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>