i965/msaa: Enable CMS layout on Gen7 for the formats that support it.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
i965: Add support for AVG instruction.

From the Ivy Bridge PRM, Vol4 Part3 p152:

    "The avg instruction performs component-wise integer average of
    src0 and src1 and stores the results in dst. An integer average
    uses integer upward rounding. It is equivalent to increment one to
    the addition of src0 and src1 and then apply an arithmetic right
    shift to this intermediate value."
i965/msaa: Modify manual_blend() to avoid unnecessary loss of precision.

When downsampling from an MSAA image to a single-sampled image, it is
inevitable that some loss of numerical precision will occur, since we
have to use 32-bit floating point registers to hold the intermediate
results while blending.  However, it seems reasonable to expect that
when all samples corresponding to a given pixel have the exact same
color value, there will be no loss of precision.

Previously, we averaged samples as follows:

    blend = (((sample[0] + sample[1]) + sample[2]) + sample[3]) / 4

This had the potential to lose numerical precision when all samples
have the same color value, since ((sample[0] + sample[1]) + sample[2])
may not be precisely representable as a 32-bit float, even if the
individual samples are.

This patch changes the formula to:

    blend = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4

This avoids any loss of precision in the event that all samples are
the same, by ensuring that each addition operation adds two equal
values.

As a side benefit, this puts the formula in the form we will need in
order to implement correct blending of integer formats.
i965/msaa: Fix integer downsampling on Gen7.

When downsampling an integer-format buffer on Gen7, we need to use the
"avg" instruction rather than the "add" instruction, to ensure that we
don't overflow the range of 32-bit integers.  Also, we need to use the
proper register type (BRW_REGISTER_TYPE_D or BRW_REGISTER_TYPE_UD) for
intermediate color data and for writing to the render target.

Note: this patch causes blorp to use the proper register type for all
operations (downsampling, upsampling, and ordinary blits).  Strictly
speaking, this is only necessary for downsampling, because the other
operations exclusively use MOV instructions on the color data.  But
it's simpler to use the proper register type in all cases.
i965/msaa: Optimize manual_blend() for compressed multisampled surfaces.

When downsampling a compressed multisampled surface, we can take a
shortcut to downsample any pixels that are were covered by a single
primitive.  In this case, the first color value we fetch is the
correct final color for the downsampled pixel, so we can skip the rest
of the downsampling operation.
i965/msaa: Configure SURFACE_STATE correctly for IMS surfaces.

This patch modifies gen7_set_surface_num_multisamples() to set up the
SURFACE_STATE appropriately for texturing from IMS format MSAA
surfaces (which are only used on Gen7 for depth and stencil buffers).
Since the function now sets more than just the number of multisamples,
it's been renamed to gen7_set_surface_msaa().

This will make it possible to remove some kludginess from the blorp
engine.
i965/msaa: Loosen assertions in compute_msaa_layout_for_pipeline.

Previously, on Gen7, compute_msaa_layout_for_pipeline() would verify
that IMS layout is not used.  However, now that we configure
SURFACE_STATE correctly for IMS surfaces, IMS layout is available.
i965/msaa: Use IMS layout when texturing from depth/stencil surfaces.

Previously, on Gen7, when texturing from a depth or stencil surface,
the blorp engine would configure the 3D pipeline as though the input
surface was non-multisampled, and perform the necessary coordinate
transformations in the fragment shader to account for the difference.
This meant outputting a lot of extra fragment shader code, and it
raised some uncertainty about how to deal with very large surfaces.

This patch modifies blorp to configure the 3D pipeline properly for
IMS layout when reading from depth and stencil surfaces.
i965/msaa: Remove comment about falsely claiming to support MSAA.

Gen6+ hardware now supports MSAA properly.
Dump image before and after blit
Control multisampling behaviour via the visual
Compute visual samples/sampleBuffers from all buffers.  TODO: validate on nVidia

+2 oglconforms.
Revert "Dump image before and after blit"

This reverts commit 022b2fb23a4435c3b1b1c6382dae22c924d1f635.
Set up sample count properly in null render buffer surface
HACK: flush after each draw operation.
Hack: always enable wm dispatch
Hack: set width/height to 128x128, as well as tiling and pitch
HACK: use ARYSPC_LOD0 for null buffer surface
HACK: disable accumulator writes in some cases
Hack: make null renderbuffer point to a WA BO