Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171128 91177308-0d34-0410-b5e6-96231b3b80d8
whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171129 91177308-0d34-0410-b5e6-96231b3b80d8
Add hasSideEffects=0 to CMP*rr_REV.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171130 91177308-0d34-0410-b5e6-96231b3b80d8
FileCheck-ize.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171131 91177308-0d34-0410-b5e6-96231b3b80d8
FileCheck-ize.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171132 91177308-0d34-0410-b5e6-96231b3b80d8
For the dwarf5 split debug info code split out the string section
per compile unit/skeleton compile unit. Update tests accordingly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171133 91177308-0d34-0410-b5e6-96231b3b80d8
Mark the divide instructions as hasSideEffects=0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171136 91177308-0d34-0410-b5e6-96231b3b80d8
Add hasSideEffects=0 to some shift and rotate instructions. None of which are currently used by code generation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171137 91177308-0d34-0410-b5e6-96231b3b80d8
Update tablegen parser to allow defm names to start with #NAME.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171140 91177308-0d34-0410-b5e6-96231b3b80d8
Move single letter 'P' prefix out of multiclass now that tablegen allows defm to start with #NAME. This makes instruction names more searchable again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171141 91177308-0d34-0410-b5e6-96231b3b80d8
Refactor DAGCombinerInfo. Change the different booleans that indicate if we are before or after different runs of DAGCo, with the CombineLevel enum.
Also, added a new API for checking if we are running before or after the LegalizeVectorOps phase. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171142 91177308-0d34-0410-b5e6-96231b3b80d8
Add hasSideEffects=0 to some forms of ROUND, RCP, and RSQRT.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171143 91177308-0d34-0410-b5e6-96231b3b80d8
AVX/AVX2: Move the code that lowers vector-trunc from a DAGCo-hook to custom lowering hook.
The vector truncs were scalarized during LegalizeVectorOps, later vectorized again by some DAGCombine optimization
and finally, lowered by a dagcombing optimization. Now, they are properly lowered during LegalizeVectorOps.
No new testcase because the original testcases still work.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171146 91177308-0d34-0410-b5e6-96231b3b80d8
On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
register. In most cases we actually compare or select YMM-sized registers
and mixing the two types creates horrible code. This commit optimizes
some of the transition sequences.

PR14657.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171148 91177308-0d34-0410-b5e6-96231b3b80d8
docs: Update the benchmark with updated perf numbers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171149 91177308-0d34-0410-b5e6-96231b3b80d8
Fix new[]/delete mismatch in FullDependence spotted by AddressSanitizer

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171150 91177308-0d34-0410-b5e6-96231b3b80d8
DAGCombinerInformation: add a getter that exposes the dagcombine level.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171152 91177308-0d34-0410-b5e6-96231b3b80d8
[ASan] Fix lifetime intrinsics handling. Now for each intrinsic we check if it describes one of 'interesting' allocas. Assume that allocas can go through casts and phi-nodes before apperaring as llvm.lifetime arguments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171153 91177308-0d34-0410-b5e6-96231b3b80d8
docs: Move link to the new "external tutorials" area.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171154 91177308-0d34-0410-b5e6-96231b3b80d8
docs: Add FAQ about "storing to a virtual register".

This came up for the N+1'st time today in IRC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171155 91177308-0d34-0410-b5e6-96231b3b80d8