Fix bit test in Exynos4210 UART emulation to use & instead of &&

* hw/exynos4210_uart.c: s/&&/&/

Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
ARM: Exynos4210: Drop gic_cpu_write() after initialization.

Remove gic_cpu_write() call after initialization that was emulating
functionality of earliest SOC bootloader which enables external
GIC CPU1 interface. Instead introduce Exynos4210-specific secondary
CPU bootloader, which enables both Internal and External GIC CPU1
interfaces.

Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/exynos4210_combiner.c: Drop excessive read/write access check.

Access to reserved area at offset higher than 0x3c is allowed in
External Combiner. Samsung Galaxy Kernel implements this. So, drop
excessive checks in read/write functions.

Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/arm_gic: Move NCPU definition to arm_gic.c

Move the NCPU definition to arm_gic.c: the maximum number
of CPU interfaces is defined by the GIC architecture specification
to be 8, so we don't need to have this #define in each of the
sources files which currently includes arm_gic.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
hw/arm_gic: Move gic_get_current_cpu into arm_gic.c

Move the gic_get_current_cpu() function into arm_gic.c.
There are only two implementations: (1) "get the index
of the currently executing CPU", used by all multicore
GICs, and (2) "always 0", used by all GICs instantiated
with a single CPU interface (the Realview board GIC and
the v7M NVIC). So we can move this into the main GIC
source file.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
hw/arm_gic: Expose PPI inputs as gpio inputs

Expose the Private Peripheral Interrupt inputs as GPIO inputs.
The layout of the GPIO array is thus:
  [0..N-1] SPIs
  [N..N+31] PPIs for CPU 0
  [N+32..N+63] PPIs for CPU 1
  ...

Treating PPIs as being another kind of input line is in line with the
GIC architecture specification, where they are clearly described that
way. The 11MPCore TRM is a bit more ambiguous, but there is no practical
difference between "set PPI X as pending" and "0->1 transition on a
PPI input line configured as edge triggered", and PPIs are always
edge triggered, so this change won't affect behaviour.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/arm_gic: Make the GIC its own sysbus device

Compile arm_gic.c as a standalone C file to produce a self contained
sysbus GIC device. Support the legacy usage by #include of the .c file
by making those users #define LEGACY_INCLUDED_GIC, so we can convert
them one by one.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
hw/a15mpcore: switch to using sysbus GIC

Switch the a15mpcore private peripheral region to using
the standalone sysbus GIC device.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/a9mpcore: Switch to using sysbus GIC

Switch the a9mpcore to using the sysbus GIC device rather
than having the a9mp private memory region device subclass
the GIC.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/realview_gic: switch to sysbus GIC

Switch the realview_gic device to the standalone sysbus GIC.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/exynos4210_gic: Convert to using sysbus GIC

Convert the Exynos GIC code to use the standalone sysbus
GIC device.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
hw/arm11mpcore: Convert to using sysbus GIC device

Convert arm11mpcore to using the standalone sysbus GIC device.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/arm_gic: Make gic_reset a sysbus reset function

Make gic_reset a sysbus reset function, so we actually
reset the GIC on system reset rather than only at init.
For the NVIC this requires us also to implement reset
of the SysTick.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/arm_gic: Use NVIC instead of LEGACY_INCLUDED_GIC define

Now all the A profile cores have been switched to use the standalone
sysbus GIC, the only remaining code which #includes arm_gic.c is
the v7M NVIC. The coupling is much closer here so it's not so
easily disentangled. For now, add a comment about how arm_gic.c
is compiled, and assume that the NVIC always includes arm_gic.c
and the non-NVIC GIC is always compiled standalone.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/arm_gic: gic_set_pending_private() is NVIC only

The function gic_set_pending_private() is now used by the NVIC
only (for the GIC we now set PPI interrupts via gpio lines and
gic_set_irq()). So make it #ifdef NVIC and remove the 'attribute
unused' annotation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/arm_gic: Remove stray hardcoded tab

Remove the single instance of a hardcoded tab from hw/arm_gic.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-xtensa: Move helpers.h to helper.h

Provides a file naming scheme consistent with other targets.

Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: improve unit tests debugging

- add testcase announcement;
- add global symbols for individual tests;
- add host-debug-* makefile target.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: QOM'ify CPU

Embed CPUXtensaState as first member of XtensaCPU.
Let CPUClass::reset() call cpu_state_reset() for now.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: QOM'ify CPU reset

Move code from cpu_state_reset() into QOM xtensa_cpu_reset().
To avoid moving reset_mmu() and dependencies, make it non-static.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>