ARM HDLCD: Add support for ARM High Definition LCD.

The ARM HDLCD device is now found in various new Versatile Express coretiles.

Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
ARM: vexpress: Add support for HDLCD on V2P-CA5s

This is a temporary solution to get everything running.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>

Conflicts:

	arch/arm/boot/dts/vexpress-v2p-ca5s.dts
	arch/arm/mach-vexpress/v2m.c

Change-Id: I805deceba0a33476e77cffa2bdfa3bc86efc7ffb
ARM: vexpress: Reduce A5 screen resolution to aid performance.

Signed-off-by: Jon Medhurst <tixy@linaro.org>
ARM: vexpress: Add support for HDLCD on V2P-CA15-TC1

This is a temporary solution to get everything running.

Signed-off-by: Jon Medhurst <tixy@linaro.org>
mmc: block: Make multi-block write errors retry as single block writes

The current mmc block code retries i/o errors on multi-block reads by
using single block reads. For platforms with unreliable multi-block
operations, like the ARM Versatile Express board, this is a valuable
error recovery path.

This patch extends the single block retry to also include write
operations.

Signed-off-by: Jon Medhurst <jon.medhurst@linaro.org>
ARM: Use TTBR1 instead of reserved context ID

On ARMv7 CPUs that cache first level page table entries (like the
Cortex-A15), using a reserved ASID while changing the TTBR or flushing
the TLB is unsafe.

This is because the CPU may cache the first level entry as the result of
a speculative memory access while the reserved ASID is assigned. After
the process owning the page tables dies, the memory will be reallocated
and may be written with junk values which can be interpreted as global,
valid PTEs by the processor. This will result in the TLB being populated
with bogus global entries.

This patch avoids the use of a reserved context ID in the v7 switch_mm
and ASID rollover code by temporarily using the swapper_pg_dir pointed
at by TTBR1, which contains only global entries that are not tagged
with ASIDs.

Reviewed-by: Frank Rowand <frank.rowand@am.sony.com>
Tested-by: Marc Zyngier <Marc.Zyngier@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
ARM: Allow ASID 0 to be allocated to tasks

Now that ASID 0 is no longer used as a reserved value, allow it to be
allocated to tasks.

Reviewed-by: Frank Rowand <frank.rowand@am.sony.com>
Tested-by: Marc Zyngier <Marc.Zyngier@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
ARM: Set bit 22 in the PL310 (cache controller) AuxCtlr register

Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

This patch ensures that bit 22 is set in the l2x0_init() function if
PL310 and not rely on the platform code to specify it. It also modifies
the 'aux' variable only if the actual register is written so that the
final printk displays the real hardware value.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Kyungmin Park <kyungmin.park@samsung.com>
ARMv7: Flush the vectors page using the base address

With the domains removal patch, the vectors page is populated using the
kernel linear mapping address. However, the flush_icache_range()
function must be called on the high vectors address because the I-cache
is allowed to have aliases (or can even be ASID-tagged VIVT). Note that
on ARMv7 processors the D-cache is non-aliasing.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: stable@vger.kernel.org
gator/daemon: Version 5.9

Signed-off-by: Jon Medhurst <tixy@linaro.org>
gator/daemon: Fix counters initialisation

In certain circumstances counter were not enabled correctly. Fixed.

Signed-off-by: Wade Cherry <wade.cherry@arm.com>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
gator/driver: Version 5.9

Signed-off-by: Jon Medhurst <tixy@linaro.org>
gator/driver: Fix build failure on Linux 3.3

Some meminfo tracepoint APIs were renamed in commit b413d48a
(mm-tracepoint: rename page-free events)

Signed-off-by: Wade Cherry <wade.cherry@arm.com>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
gator/driver: Makefile fix for output path of generated file gator_events.h

Signed-off-by: Jon Medhurst <tixy@linaro.org>
gator/driver: Makefile fixes for building in-tree

Signed-off-by: Jon Medhurst <tixy@linaro.org>
gator/driver: Add config for building the module in-tree

Signed-off-by: Jon Medhurst <tixy@linaro.org>
serial: PL011: move interrupt clearing

Commit 360f748b204275229f8398cb2f9f53955db1503b
"serial: PL011: clear pending interrupts"
attempts to clear interrupts by writing to a
yet-unassigned memory address. This fixes the issue.

The breaking patch is marked for stable so should be
carried along with the other patch.

Cc: Shreshtha Kumar Sahu <shreshthakumar.sahu@stericsson.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: stable <stable@vger.kernel.org>
Reported-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
gator/driver: Replace d_alloc_root() with d_make_root()

d_alloc_root() was removed in 3.4

Signed-off-by: Jon Medhurst <tixy@linaro.org>
Merge branch 'tracking-armlt-mmc' into integration-linux-vexpress
Merge branch 'tracking-armlt-misc-fixes' into integration-linux-vexpress