omap: hwmod: enable clocks before deasserting hardreset

The enable code currently deasserts the hard-reset before
turning on the clocks. These kind of reset lines are limited
only to processor-device like IPs such as DSP or IPU or
IVA, which actually need the clock to be enabled first.

The code that deasserts the hard-reset has therefore been
relocated to execute after the clocks are enabled, to avoid
the hard-deassert traces (failed to hard reset).

Change-Id: Id9c413b315c927295cf4be7f986f6e1a710b9ef8
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Juan Gutierrez <jgutierrez@ti.com>
Signed-off-by: Oleg Matcovschi <oleg.matcovschi@ti.com>
Signed-off-by: Paul Hunt <hunt@ti.com>
OMAP4: clocks: skip module idle status check for processor devices

The module idle status for processor devices (hwmod devices) like IPU,
DSP & IVA will fail the functional status check as long as the module
is held in reset. The status would always show that the module is in
transition, and would complete only after the relevant hwmod's reset
line is deasserted.

The initialization sequence for these processor devices require the
clocks to be enabled first before deasserting the reset lines. This
would cause a failure in _omap4_module_wait_ready which checks for
the module idle status to be functional. The clk ops for dsp, ipu
and iva in the clock data has therefore been redefined such that
the module idlest status check in the clock enable code is skipped
over.

Change-Id: I799b30c5f86e51739a56538f602a8030fd4bdb09
Signed-off-by: Oleg Matcovschi <oleg.matcovschi@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Juan Gutierrez <jgutierrez@ti.com>
Signed-off-by: Paul Hunt <hunt@ti.com>
omap-hsmmc: Implementation of i761 errata

Errata description:
Due to a bad behavior of an internal signal, the Card Error interrupt bit
MMCHS_STAT[28] CERR may not be set sometimes when an error occurred in the
card response.

Workaround:
After responses of type R1/R1b for all cards and responses of type R5/R5b/R6
for SD and SDIO cards, software must read two registers: MMCHS_RSP10 and
MMCHS_CSRE. When a MMCHS_CSRE[i] bit is set to 1, if the corresponding bit at
the same position in the response MMCHS_RSP10[i] is set to 1, the host
controller indicates a card error and software should proceed in the same way
as if a CERR interrupt would have been detected in the MMCHS_STAT register.

Note:
This errata is applicable for omap44xx.

Change-Id: Ib024bfb0624df04b7d6c61c129cbd9a34f919814
Signed-off-by: Semen Protsenko <semen.protsenko@ti.com>
OMAP: UART: Enable RTS line control in UART driver

On suspend path single data byte can be losted by UART.
For prevent the issue we need to enable RTS control in
UART driver. Rising the RTS line right after suspend
routine start preventing send additional data from client
and thereby preventing data lost.
Since this featute was already implemented in UART driver
and depends of platfrom setting that doing this via
platform data and just for UART1.

Change-Id: I4cb3f5da3b5719a1d4f7b902d73272e99eeae8ac
Signed-off-by: Volodymyr Riazantsev <v.riazantsev@ti.com>
OMAP4: ST: Disabling UART if ldisc not installed.

In cases when there is no line discipline to be installed UART chip must be
disabled.

Rationale: if ldisc is not installed so it can't be uninstalled.
Thus UART chip still enabled and we have wakelock for it
(see plat_uart_enable() function in both blaze and 44xx-tablet board files).
In that case we can't go in suspend mode.

Motivation: when using busybox ramdisk (e.g. for testing kernel w/o AFS) we
have no ldisc that causes impossibility to go to suspend mode.

Change-Id: I6fac0b9411ed765e8e598328b89a41a50b5fbfea
Signed-off-by: Semen Protsenko <semen.protsenko@ti.com>
OMAP: I2C: Disable interrupts in omap_i2c_bus_clear()

Interrupts that occur during omap_i2c_bus_clear() can cause to
erroneous behaviour in interrupt handler, i.e. multiple printing of
"RRDY IRQ while no data requested" message. So disable interrupts
in omap_i2c_bus_clear() function since they can't be handled correctly.

Change-Id: If4525c93284766d0a2705d7ca4d1f962e3cc4b15
Signed-off-by: Semen Protsenko <semen.protsenko@ti.com>
OMAP4: PM: Fix missed PRCM MPU interrupt events

OMAP PRCM detects events with EDGE sensitivity. Edge sensitivity
requires to clear the interrupt event status bit before acknowledging
the source event.
If the source event is cleared (1) before reseting the interrupt event
status bit (2), then a subsequent source event (i.e edge) between (1)
and (2) would be missed. Then, all the source events would be kept
"masked" until the source event is cleared again.

The bug seen here is that upon two consecutive PRCM interrupt events
from the IO daisy chain source event, the second event is missed if it
occurs before the PRCM interrupt event status is cleared.
Since the IO daisy chain source event has not been acknowledged, the
subseqent events from this source are missed too.

This patch fix the PRCM interrupt handler by acknowledging the interrupt
event status bit before clearing the source event.

Change-Id: I8c43a93c3b6c7c654ddaa262b7c1c3e7385da158
Signed-off-by: Patrick Combes <p-combes@ti.com>
Signed-off-by: Cedric Poignet <c-poignet@ti.com>
OMAP: hwmod: Don't update sysc cache on soft-reset

When the module is resetted using via SYSCONFIG.SOFTRESET the following
sequence causes SYSC cache value to be updated:
omap_hwmod_softreset()
 |-->_write_sysconfig()

_ocp_softreset
 |-->_write_sysconfig()

As result, when the module is enabled next time the SYSC cache value
with SYSCONFIG.SOFTRESET=1 will be used by _enable_sysc() and that
will cause unexpected reset of module. This commit prevents SYSC
cache updating during soft reset.

New static function _write_sysconfig_raw() is introduced for writing
value to the module's OCP_SYSCONFIG register without cache updating.

Change-Id: I0058740c2888c23648a498597142a5c0d1b550ba
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
OMAP4: board: power: Set sense resistor value for current measurement

This patch sets resistor value (10 mOhm) for current measurement in
the board file for Blaze and Tablet/Tablet2.

Change-Id: I041a45fce65075d721b1f37ec9d3fb7ab3ac4565
Signed-off-by: Oleksandr Dmytryshyn <oleksandr.dmytryshyn@ti.com>
blaze_defconfig: Enable CONFIG_TUN, CONFIG_CRC32

Google's CTS 4.0.3_r3 is requiring TUN/TAP driver to be present
in kernel. Option CONFIG_CRC32 is enabled as dependency.

Change-Id: I24f1eabfcc40b8ed609fc8f09059984f7129d823
Signed-off-by: Andrii Beregovenko <a.beregovenko@ti.com>
OMAPDSS: DSS: Add MEM2MEM manager mode

This change adds memory-to-memory (M2M) mode with using of the
manager. The main idea is to connect write back (WB) pipeline to
the manager (overlay, in terms of technical reference manual)
which is not in use (physical interface is turned-off) for using
advantages of hardware manager in M2M mode. In this case several
pipelines can be connected to the manager.

Change-Id: Ifa649bd5b18f54f3ce583fdee802c799b2c30711
Co-author: Sergiy Kibrik <sergiikibrik@ti.com>
Signed-off-by: Mykhailo Denysiuk <x0172934@ti.com>
OMAPDSS: DSSCOMP: Add MEM2MEM with manager mode

This change adds code for maintain MEM2MEM with manager mode
at DSSCOMP level.

Change-Id: Id14bc0c4884310250b6709436d815c9102a9d72e
Signed-off-by: Mykhailo Denysiuk <x0172934@ti.com>
OMAPDSS: DSS: workaround for errata i642

This change adds workaround for errata i642.

Description of Errata i642:
VID /GFX Pipeline Underflow Interrupt Generated When In WB
Memory-to-memory Operation. Errata ID: i642.

Recommended workaround:
Software should disable the VID/GFX pipeline underflow interrupt
by writing 0x0 in DISPC_IRQENABLE[20-12-10-6] bit if it is
connected to the WB pipeline in memory-to-memory mode.
Software should not consider the underflow interrupt generated in
DISPC_IRQSTATUS[20-12-10-6] bit when in memory-to-memory mode.

This change do not disable interrupt, but ignores its handler in
case if pipeline connected to the manager, which is used in MEM2MEM
mode.

Silicon Versions Impacted:
OMAP4430 ES1.0, ES2.0, ES2.1, ES2.2, ES2.3
OMAP4460 ES1.0, ES1.1
OMAP4470 ES1.0

Change-Id: If7532b1b7454d92a648673b6da29cc31448519ab
Author: Rohit Choraria <rohitkc@ti.com>
Co-author: Mykhailo Denysiuk <x0172934@ti.com>
Signed-off-by: Mykhailo Denysiuk <x0172934@ti.com>
OMAPDSS: DSS: fix for black frames in mem2mem mode

This change fixes black frames issue in MEM2MEM mode.
The root of the problem is in apply_irq_handler function, which
time-to-time is called between calls to omap_dss_wb_apply() and
omap_dss_mgr_apply() functions. So, apply_irq_handler sometimes
is called when WB cache was updated, but managr cache and others
caches were not updated yet.

Change-Id: I308f5ef7d7b6e790382c22c40b8cddedaf91308e
Signed-off-by: Rohit Choraria <rohitkc@ti.com>
Signed-off-by: Mykhailo Denysiuk <x0172934@ti.com>
Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>
OMAP4: Tablet: Set correct pixel clock value

Set the correct pixel clock value for the Samsung/Hydis
WUXGA display.

Change-Id: I133380f6332f1e90d77e9257c9e29151201c1252
Signed-off-by: Peter Nordström <nordstrom@ti.com>
Merge branch 'p-android-omap-3.0' of git://git.omapzoom.org/kernel/omap into 4AI.5-dev