palmas no need to ignore ldo2 ldo8 any more

Signed-off-by: Andy Green <andy.green@linaro.org>
omap45 remove no arm smp twd conflict in kconfig

Signed-off-by: Andy Green <andy.green@linaro.org>
config include 44xx in omap5evm

Signed-off-by: Andy Green <andy.green@linaro.org>
i2c omap nuke hwspinklock code

Signed-off-by: Andy Green <andy.green@linaro.org>
omap5 comap4 compat allow no l2cache base

Signed-off-by: Andy Green <andy.green@linaro.org>
omap4 hwmod kill emif hwmod

Omap4 boot blows these otherwise

[    0.000000] WARNING: at /projects/linaro/linux-2.6/arch/arm/mach-omap2/omap_hwmod.c:2069 omap_hwmod_register+0x48/0x68()
[    0.000000] omap_hwmod: emif1: _register returned -22
[    0.000000] Modules linked in:
[    0.000000] Backtrace:
[    0.000000] [<c0011fd8>] (dump_backtrace+0x0/0x110) from [<c04344c8>] (dump_stack+0x18/0x1c)
[    0.000000]  r6:c05115cb r5:00000815 r4:c05cbf40 r3:600001d3
[    0.000000] [<c04344b0>] (dump_stack+0x0/0x1c) from [<c0039074>] (warn_slowpath_common+0x54/0x6c)
[    0.000000] [<c0039020>] (warn_slowpath_common+0x0/0x6c) from [<c0039130>] (warn_slowpath_fmt+0x38/0x40)
[    0.000000]  r8:8000406a r7:bfffffff r6:c05cbfd4 r5:c05bfccc r4:c05bfcd0
[    0.000000] r3:00000009
[    0.000000] [<c00390f8>] (warn_slowpath_fmt+0x0/0x40) from [<c059665c>] (omap_hwmod_register+0x48/0x68)
[    0.000000]  r3:c051667c r2:c0511b90
[    0.000000] [<c0596614>] (omap_hwmod_register+0x0/0x68) from [<c0599c14>] (omap44xx_hwmod_init+0x14/0x1c)
[    0.000000]  r5:c0613090 r4:c05b5814
[    0.000000] [<c0599c00>] (omap44xx_hwmod_init+0x0/0x1c) from [<c059415c>] (omap4430_init_early+0x24/0x30)
[    0.000000] [<c0594138>] (omap4430_init_early+0x0/0x30) from [<c05900ac>] (setup_arch+0x138/0x184)
[    0.000000] [<c058ff74>] (setup_arch+0x0/0x184) from [<c058c5e0>] (start_kernel+0x88/0x304)
[    0.000000]  r6:00000000 r5:00000001 r4:c05ca000
[    0.000000] [<c058c558>] (start_kernel+0x0/0x304) from [<80008044>] (0x80008044)
[    0.000000]  r7:c05d0844 r6:c05b6c24 r5:c05cc550 r4:10c5387d
[    0.000000] ---[ end trace 1b75b31a2719ed1c ]---
[    0.000000] ------------[ cut here ]------------
[    0.000000] WARNING: at /projects/linaro/linux-2.6/arch/arm/mach-omap2/omap_hwmod.c:2069 omap_hwmod_register+0x48/0x68()
[    0.000000] omap_hwmod: emif2: _register returned -22
[    0.000000] Modules linked in:
[    0.000000] Backtrace:
[    0.000000] [<c0011fd8>] (dump_backtrace+0x0/0x110) from [<c04344c8>] (dump_stack+0x18/0x1c)
[    0.000000]  r6:c05115cb r5:00000815 r4:c05cbf40 r3:600001d3
[    0.000000] [<c04344b0>] (dump_stack+0x0/0x1c) from [<c0039074>] (warn_slowpath_common+0x54/0x6c)
[    0.000000] [<c0039020>] (warn_slowpath_common+0x0/0x6c) from [<c0039130>] (warn_slowpath_fmt+0x38/0x40)
[    0.000000]  r8:8000406a r7:bfffffff r6:c05cbfd4 r5:c05bfcd0 r4:c05bfcd4
[    0.000000] r3:00000009
[    0.000000] [<c00390f8>] (warn_slowpath_fmt+0x0/0x40) from [<c059665c>] (omap_hwmod_register+0x48/0x68)
[    0.000000]  r3:c0516682 r2:c0511b90
[    0.000000] [<c0596614>] (omap_hwmod_register+0x0/0x68) from [<c0599c14>] (omap44xx_hwmod_init+0x14/0x1c)
[    0.000000]  r5:c0613090 r4:c05b5814
[    0.000000] [<c0599c00>] (omap44xx_hwmod_init+0x0/0x1c) from [<c059415c>] (omap4430_init_early+0x24/0x30)
[    0.000000] [<c0594138>] (omap4430_init_early+0x0/0x30) from [<c05900ac>] (setup_arch+0x138/0x184)
[    0.000000] [<c058ff74>] (setup_arch+0x0/0x184) from [<c058c5e0>] (start_kernel+0x88/0x304)
[    0.000000]  r6:00000000 r5:00000001 r4:c05ca000
[    0.000000] [<c058c558>] (start_kernel+0x0/0x304) from [<80008044>] (0x80008044)
[    0.000000]  r7:c05d0844 r6:c05b6c24 r5:c05cc550 r4:10c5387d
[    0.000000] ---[ end trace 1b75b31a2719ed1d ]---


Signed-off-by: Andy Green <andy.green@linaro.org>
omap5 omap4 dont register twl4030 if not 44xx

Signed-off-by: Andy Green <andy.green@linaro.org>
omap5 add ifdef for camera init

Signed-off-by: Andy Green <andy.green@linaro.org>
omap45 dvfs abb react well if given error instead of target voltage pointer

Signed-off-by: Andy Green <andy.green@linaro.org>
omap45 device restore revision check to earlier in boot

The revision check got moved to much late during the Omap 4-5 integration
upheaval.

Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
config 5432

Signed-off-by: Andy Green <andy.green@linaro.org>
OMAP5: Init sram from omap_sdrc_init like other archs

_omap2_map_common_io has been deprecated upstream by patch
   a66cb345 "ARM: OMAP: Map SRAM later on with ioremap_exec()"
Make OMAP5 toe the same line.

Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
ARM: OMAP2+: omap_device: call all suspend, resume callbacks when OMAP_DEVICE_NO_IDLE_ON_SUSPEND is set

During system suspend, when OMAP_DEVICE_NO_IDLE_ON_SUSPEND is set on
an omap_device, call the corresponding driver's ->suspend() and
->suspend_noirq() callbacks (if present).  Similarly, during resume,
the driver's ->resume() and ->resume_noirq() callbacks must both be
called, if present.  (The previous code only called ->suspend_noirq()
and ->resume_noirq().)

If all of these callbacks aren't called, some important driver
suspend/resume code may not get executed.

In current mainline, the bug fixed by this patch is only a problem
under the following conditions:

- the kernel is running on an OMAP4

- an OMAP UART is used as a console

- the kernel command line parameter 'no_console_suspend' is specified

- and the system enters suspend ("echo mem > /sys/power/state").

Under this combined circumstance, the system cannot be awakened via
the serial port after commit be4b0281956c5cae4f63f31f11d07625a6988766c
("tty: serial: OMAP: block idle while the UART is transferring data in
PIO mode").  This is because the OMAP UART driver's ->suspend()
callback is never called.  The ->suspend() callback would have called
uart_suspend_port() which in turn would call enable_irq_wake().  Since
enable_irq_wake() isn't called for the UART's IRQ, check_wakeup_irqs()
would mask off the UART IRQ in the GIC.

On v3.3 kernels prior to the above commit, serial resume from suspend
presumably occurred via the PRCM interrupt.  The UART was in
smart-idle mode, so it was able to send a PRCM wakeup which in turn
would be converted into a PRCM interrupt to the GIC, waking up the
kernel.  But after the above commit, when the system is suspended in
the middle of a UART transmit, the UART IP block would be in no-idle
mode.  In no-idle mode, the UART won't generate wakeups to the PRCM
when incoming characters are received; only GIC interrupts.  But since
the UART driver's ->suspend() callback is never called,
uart_suspend_port() and enable_irq_wake() is never called; so the UART
interrupt is masked by check_wakeup_irqs() and the UART can't wake up
the MPU.

The remaining mechanism that could have awakened the system would have
been I/O chain wakeups.  These wouldn't be active because the console
UART's clocks are never disabled when no_console_suspend is used,
preventing the full chip from idling.  Also, current mainline doesn't
yet support full chip idle states for OMAP4, so I/O chain wakeups are
not enabled.

This patch is the result of a collaboration.  John Stultz
<johnstul@us.ibm.com> and Andy Green <andy.green@linaro.org> reported
the serial wakeup problem that led to the discovery of this problem.
Kevin Hilman <khilman@ti.com> narrowed the problem down to the use of
no_console_suspend.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: John Stultz <johnstul@us.ibm.com>
Cc: Andy Green <andy.green@linaro.org>
Cc: Kevin Hilman <khilman@ti.com>
omap4plus scm stop crash on suspend

Signed-off-by: Andy Green <andy.green@linaro.org>
ti st kim stop crash on suspend

Signed-off-by: Andy Green <andy.green@linaro.org>
omap4 clocks detect clock rounding error

Signed-off-by: Andy Green <andy.green@linaro.org>
omap2plus clock fix dcc error path and solve random crashes

This corrects dcc state if there is an error in dpll_set_rate.

It also migrates dcc setting to AFTER clock setting on >1GHz case.

This is necessary to stop random crashes when cpufreq does this code.

Signed-off-by: Andy Green <andy.green@linaro.org>
omap4460: Fix core domain frequency

Signed-off-by: Sebastien Jan <s-jan@ti.com>
omap4430: disable OPP50 support for core and iva

Prevent core and iva voltage domains from scaling (they will remain
in OPP100).
This will prevent borders effects while constrains and notification
frameworks are not in place (ex: avoid scaling down core if an high
L3 bdw is requried).

MPU can still scale, which is sufficient for thermal considerations.
But SGX, IVA, Ducati and L3 won't scale anymore and stay at OPP100.

Signed-off-by: Sebastien Jan <s-jan@ti.com>
omap4 clocks allow 1MHz leeway

With smartreflex(?) pll settings no long always match exactly
this allows match on up to 1MHz lower frequency.

Signed-off-by: Andy Green <andy.green@linaro.org>