ARM: mm: cache-l2x0: Correct l2x0 initialization

This corrects the regression in the msm-2.6.35 version
of this file. The initialization routine was not setting
L2X0_AUX_CTRL and missing an INV_WAY flush as specified
in the tech documents.

Change-Id: I9215fcf4acc6655f0eec82f1ef05406493e38d7d
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
proc-v7.S : Fix MMU disabling in cpu_v7_reset

Using the virt_to_phys macro to map the cpu_v7_reset stub into
1:1 mapping when disabling MMU and flushing caches

Change-Id: Idedc31c96dc8708632586542396c54b6238d6f77
Signed-off-by: David Keitel <dkeitel@codeaurora.org>
arm: mm: add CONFIG_STRICT_MEMORY_RWX

If this is set, kernel text will be made RX, kernel data and stack
RW, rodata R so that writing to kernel text, executing kernel data
or stack, or writing to read-only data or kernel text will not
succeed.

Change-Id: Ib80907b34388bf547c4f268a903a766acaab9ae2
Signed-off-by: Larry Bassel <lbassel@codeaurora.org>

Conflicts:

	arch/arm/mm/Kconfig
arm: mm: restrict kernel memory permissions if CONFIG_STRICT_MEMORY_RWX set

If CONFIG_STRICT_MEMORY_RWX is set, make kernel text RX,
kernel data/stack RW and rodata RO so that writing
on kernel text, executing kernel data or stack, or
writing on or executing read-only data is prohibited.

Change-Id: Ib2242c20dabddb63ef3f5655d5794fe418cb6287
Signed-off-by: Larry Bassel <lbassel@codeaurora.org>
ARM: Improve the L2 cache performance when PL310 is used

With this L2 cache controller, the cache maintenance by PA and sync
operations are atomic and do not require a "wait" loop. This patch
conditionally defines the cache_wait() function.

Since L2x0 cache controllers do not work with ARMv7 CPUs, the patch
automatically enables CACHE_PL310 when only CPU_V7 is defined.

Change-Id: I70fbf1023c128e0296e3d9ef3c9fe2b5bc59c7b9
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
arm: fix misleading message when CONFIG_STRICT_MEMORY_RWX set

If CONFIG_STRICT_MEMORY_RWX is set, a message was printed
that access was being restricted for bank 0, rather than
in general.

Change-Id: I7dbfecdde9a0e4a4724238567e9170dde30c05bf
Signed-off-by: Larry Bassel <lbassel@codeaurora.org>
arm: map reserved memory RW if CONFIG_STRICT_MEMORY_RWX set

If CONFIG_STRICT_MEMORY_RWX is set, make the virtual to
physical mapping for address ranges reserved for hotpluggable
memory RW instead of RWX.

Change-Id: Id18928400f258aa90b027874cb719c4c7d5d7335
Signed-off-by: Larry Bassel <lbassel@codeaurora.org>

Conflicts:

	arch/arm/mm/init.c
ARM: l2x0: Add cache ID for L220 part

Add cache ID for L220 part and re-organize the code for outercache
functions assignment.

Change-Id: I251e9fe2ca583f2c77542e3d5a13d19558900cff
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>

Conflicts:

	arch/arm/include/asm/hardware/cache-l2x0.h
	arch/arm/mm/cache-l2x0.c
arm: Implement l2x0 cache disable functions

Add flush_all, inv_all and disable functions to the l2x0 code. These
functions are called from kexec code to prevent random crashes in the
new kernel.

Platforms like OMAP which control L2 enable/disable via SMI mode can
override the outer_cache.disable() function to implement their own.

Change-Id: If278124a513a4da984467bb927269f314d689ab3
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Linus Walleij <linus.walleij@stericsson.com>
[l2x0_flush_all adjustments by Trilok Soni <tsoni@codeaurora.org>]
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>

Conflicts:

	arch/arm/mm/cache-l2x0.c
ARM: l2x0: Determine the cache size

The cache size is needed for to optimise range based
maintainance operations

Change-Id: I9acbb931a594ce770694927712f8f674c648d988
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
ARM: l2x0: Optimise the range based operations

For the big buffers which are in excess of cache size, the maintaince
operations by PA are very slow. For such buffers the maintainace
operations can be speeded up by using the WAY based method.

Change-Id: I4b8d110ed980e72fb7f23c6408f80b871dc64e24
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>