New stats counters for OOO core

These counters are added to support MCPAT power models

Signed-off-by: Avadh Patel <avadh4all@gmail.com>
New Script marss2mcpat.py

This script convert Marss's YAML output file to MCPAT's XML input file to
generate power numbers

Signed-off-by: Avadh Patel <avadh4all@gmail.com>
Small fix in McPat script

Signed-off-by: Avadh Patel <avadh4all@gmail.com>
Dump Simulated Machine Configuration

This huge patch introduces new feature that dumps the simulated machine
configuration to either logfile or user specified file for later reference.
Configuration is dumped in YAML format so other tools/scripts can easily parse
the configuration.

Signed-off-by: Avadh Patel <avadh4all@gmail.com>
Added a comment in Cpu Controller configuration dump

To indicate that this structure is purly related to software and has no
relevance to any hardware module.

Signed-off-by: Avadh Patel <avadh4all@gmail.com>
Per core memory request pool

Changed to per core memory request pool from one global pool.
This eliminates locking the request pool.

Signed-off-by: Avadh Patel <avadh4all@gmail.com>

Conflicts:

	ptlsim/cache/memoryHierarchy.cpp
	ptlsim/cache/memoryRequest.cpp
Bug fix in 'ret' instruction

This fix set the 'riptaken' and 'ripseq' values of 'ret' opcode so
branch-predictor doesn't generate any invalid RIP address.

Signed-off-by: Avadh Patel <avadh4all@gmail.com>
Merge branch 'master' into features
Fix INT3 instruction

Signed-off-by: Avadh Patel <avadh4all@gmail.com>
Merge branch 'master' into features
New cmdline option '-s' in run_bench.py

Using -s or --simconfig switch users can override/add simconfig options to
simulation runs.  Also this patch now creates the 'simconfig' files in the same
output directory where log files are stored so user can find out later that
what were the configuration parameters.

Signed-off-by: Avadh Patel <avadh4all@gmail.com>
Changed simconfig file name based on log file name in run_bench.py

Signed-off-by: Avadh Patel <avadh4all@gmail.com>
Added 'writeback' or 'writethrough' configuration dump

Signed-off-by: Avadh Patel <avadh4all@gmail.com>
Increased QEMU periodic timer delay in simulation mode

This change increses the periodic timer setup and run in QEMU for handling
external IO events.  This timer is delayed because in simulation mode VM's
speed is around 200 to 400 KHz and we don't want to generate interrupts too
quickly.

Signed-off-by: Avadh Patel <avadh4all@gmail.com>
Disable compiling on 32 bit machines

Signed-off-by: Avadh Patel <avadh4all@gmail.com>
Added directory entry locking support

To avoid dead lock issues in directory.

Signed-off-by: Avadh Patel <avadh4all@gmail.com>
Merge branch 'master' into features
Fix in split-bus broadcast-complete signal

This change avoids simulation crashes for scenarios where controller queue gets
full between broadcast and broadcast-complete cycles.

Signed-off-by: Avadh Patel <avadh4all@gmail.com>
Clear request that doesn't have destination set

In cacheController clear the request that doesn't have destination interconnect
set so it doesn't cause any deadlocks.

Signed-off-by: Avadh Patel <avadh4all@gmail.com>
Support 64 bit store to memory in FIST instruciton

Signed-off-by: Avadh Patel <avadh4all@gmail.com>