Move get_draw_offsets from brw_blorp_mip_info to a global location (TODO: maybe remove?)
i965/blorp: store surface width/height in brw_blorp_mip_info.

Previously, gen{6,7}_blorp_emit_surface_state would look up the width
and height of the surface at the time they set up the surface state,
and then tweak it if necessary (because a W-tiled surface is being
mapped as Y-tiled).  With this patch, we look up the width and height
when setting up the blit, and store them in brw_blorp_mip_info.  This
allows us to do the necessary tweak in the brw_blorp_blit_params
constructor (where it makes more sense).  It also reduces the need to
keep track of level and layer in brw_blorp_mip_info, so that a future
patch can eliminate them entirely.

For consistency, this patch makes a similar change to the handling of
depth buffers when doing HiZ operations.
i965/blorp: store x and y offsets in brw_blorp_mip_info.

Currently, gen{6,7}_blorp_emit_surface_state assumes that the src and
dst surfaces are mapped to miplevel 0 and layer 0 (thus no surface
offset is required).  This is a bug, since the user might try to blit
to and from levels/layers other than 0.

To fix this bug, it will not be sufficient to have
gen6_{6,7}_blorp_emit_surface_state look up the surface offset at the
time they set up the surface state, since these offsets will need to
be tweaked when blitting stencil buffers (due to the fact that stencil
buffer blits have to swizzle between W and Y tiling formats).

So, to pave the way for the bug fix, this patch causes the x and y
offsets to be computed during blit setup and stored in
brw_blorp_mip_info.

As a result of this change, brw_blorp_mip_info doesn't need to store
the level and layer anymore.

For consistency, this patch makes a similar change to the handling of
depth buffers when doing HiZ operations.
i965/blorp: Thread level and layer through brw_blorp_blit_miptrees().

Previously, when performing a blit using the blorp engine, we failed
to account for the level and layer of the source and destination.  As
a result, all blits would occur between miplevel 0 and layer 0 of the
corresponding textures, regardless of which level/layer was bound to
the framebuffer.

This patch passes the correct level and layer through
brw_blorp_miptrees() into the brw_blorp_blit_params data structure.

Further patches in the series will adapt
gen{6,7}_blorp_emit_surface_state to make use of these parameters.
i965/blorp: Account for offsets when emitting SURFACE_STATE.

Fixes piglit tests "framebuffer-blit-levels {read,draw} depth".
intel: Add map_stencil_as_y_tiled to intel_region_get_tile_masks
intel: Add map_stencil_as_y_tiled to intel_region_get_aligned_offset
i965/blorp: don't reduce stencil alignment restrictions when multisampling.

When blitting to a stencil buffer, we need to align the rectangle we
send down the rendering pipeline, to account for the fact that the
stencil buffer uses a W-tiled layout, but we are configuring its
surface state as Y-tiled.

Previously, when the stencil buffer was multisampled, we assumed that
we could reduce the amount of alignment that was necessary, since each
pixel occupies a block of 2x2 or 4x2 samples in the stencil buffer.
That would have been correct if the coordinates we were adjusting were
measured in pixels.  However, the conversion from pixel coordinates to
coordinates within the interleaved buffer has already been done;
therefore the full alignment restriction applies.

Note: the reason this mistake wasn't previously uncovered by piglit
tests is because it is being masked by another mistake: the blorp
engine is using overly conservative alignment restrictions when doing
stencil blits.  The overly conservative alignment restrictions will be
removed in the patch that follows.  Doing this fix now will prevent
the subsequent patch from introducing regressions.
i965/blorp: Reduce alignment restrictions for stencil blits.

Previously, we aligned all stencil blit operations to multiples of the
size of a tile, since stencil buffers use W-tiling, and blorp has to
approximate this by configuring the 3D pipeline for Y-tiling and
swizzling coordinates.

However, this was unnecessarily conservative; it turns out that the
differences between W-tiling and Y-tiling are confined to 32-byte
sub-tiles within the 4k tiling pattern; the layout of these 32-byte
sub-tiles within the larger 4k tile is the same (8 sub-tiles across by
16 sub-tiles down, in column-major order).  Therefore we only need to
align stencil blit operations to multiples of the sub-tile size.

Note: although the performance improvement of this change is probably
quite small, the fact that W-tiling and Y-tiling formats only differ
within 32-byte sub-tiles will be essential in a future patch to ensure
that stencil blits work correctly between parts of the miptree other
than level/layer 0.  Making this change provides handy documentation
(and validation) of this fact.
i965/blorp: Fix offsets and width/height for stencil blits.
HACK: show offsets
HACK: disable HW blitter for better testing of blorp
i965/gen6+: Adjust stencil buffer size after computing miptree layout.

Since Gen6+ stencil buffers use W-tiling (a tiling arrangement which
drm and the kernel are not aware of) we need to round up the width and
height of a stencil buffer to multiples of the W-tile size (64x64)
before allocating a stencil buffer.  Previously, we rounded up the
size of the base miplevel, and then computed the miptree layout based
on the rounded up size.  This was incorrect, because it meant that the
total size of the miptree would not be properly W-tile aligned, and
therefore we would not always allocate enough pages.

For example, on Sandy Bridge, when allocating a mipmapped stencil
texture of size 128x128, we would first round up to the nearest
multiple of 64x64 (causing no change to the size), and then compute
the miptree layout (whose size worked out to 128x196).  Then we would
request an allocation of 128*196 bytes (6.125 pages), causing 7 pages
to be allocated to the texture.  However, the texture needs 8 pages,
since each W-tile occupies a page, and it takes 2 W-tiles to cover a
width of 128 and 4 W-tiles to cover a height of 196.

This patch changes the order of operations so that the miptree layout
is computed first and then the total size of the miptree is rounded up
to be W-tile aligned.

NOTE: This is a candidate for stable release branches.
intel: avoid undefined variable warnings in intel_screen.c