Remove unused argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165636 91177308-0d34-0410-b5e6-96231b3b80d8
Specify CPU model to avoid breaking ATOM builds



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165638 91177308-0d34-0410-b5e6-96231b3b80d8
Remove dead variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165639 91177308-0d34-0410-b5e6-96231b3b80d8
Add the testcase from pr13254 (the old scalarreply pass handles this wrong;
the new sroa pass handles it right).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165644 91177308-0d34-0410-b5e6-96231b3b80d8
tblgen: Put dyn_cast<> machinery in place for Init hierarchy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165645 91177308-0d34-0410-b5e6-96231b3b80d8
tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.

Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>.
That will happen in a future patch.

There are also two dyn_cast_or_null<>'s slipped in instead of
dyn_cast<>'s, since they were causing crashes with just dyn_cast<>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165646 91177308-0d34-0410-b5e6-96231b3b80d8
tblgen: Use semantically correct RTTI functions.

Also, some minor cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165647 91177308-0d34-0410-b5e6-96231b3b80d8
tblgen: Move mini Type hierarchy to LLVM-style RTTI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165648 91177308-0d34-0410-b5e6-96231b3b80d8
tblgen: Compile TableGen without RTTI.

TableGen no longer needs RTTI!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165651 91177308-0d34-0410-b5e6-96231b3b80d8
Remove unnecessary RTTI from the build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165652 91177308-0d34-0410-b5e6-96231b3b80d8
Revert r165652: "Remove unnecessary RTTI from the build."

... Apparently the RTTI is still necessary for some reason.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165654 91177308-0d34-0410-b5e6-96231b3b80d8
Add in support for expansion of all of the comparison operations to the absolute minimum required set. This allows a backend to expand any arbitrary set of comparisons as long as a minimum set is supported.
The minimum set of required instructions is ISD::AND, ISD::OR, ISD::SETO(or ISD::SETOEQ) and ISD::SETUO(or ISD::SETUNE). Everything is expanded into one of two patterns:
Pattern 1: (LHS CC1 RHS) Opc (LHS CC2 RHS)
Pattern 2: (LHS CC1 LHS) Opc (RHS CC2 RHS)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165655 91177308-0d34-0410-b5e6-96231b3b80d8
The PowerPC VRSAVE register has been somewhat of an odd beast since
the Altivec extensions were introduced.  Its use is optional, and
allows the compiler to communicate to the operating system which
vector registers should be saved and restored during a context switch.
In practice, this information is ignored by the various operating
systems using the SVR4 ABI; the kernel saves and restores the entire
register state.  Setting the VRSAVE register is no longer performed by
the AIX XL compilers, the IBM i compilers, or by GCC on Power Linux
systems.  It seems best to avoid this logic within LLVM as well.

This patch avoids generating code to update and restore VRSAVE for the
PowerPC SVR4 ABIs (32- and 64-bit).  The code remains in place for the
Darwin ABI.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165656 91177308-0d34-0410-b5e6-96231b3b80d8
When generating spill and reload code for vector registers on PowerPC,
the compiler makes use of GPR0.  However, there are two flavors of
GPR0 defined by the target:  the 32-bit GPR0 (R0) and the 64-bit GPR0
(X0).  The spill/reload code makes use of R0 regardless of whether we
are generating 32- or 64-bit code.

This patch corrects the problem in the obvious manner, using X0 and
ADDI8 for 64-bit and R0 and ADDI for 32-bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165658 91177308-0d34-0410-b5e6-96231b3b80d8
Patch by Shuxin Yang <shuxin.llvm@gmail.com>.

Original message:

The attached is the fix to radar://11663049. The optimization can be outlined by following rules:

   (select (x != c), e, c) -> select (x != c), e, x),
   (select (x == c), c, e) -> select (x == c), x, e)
where the <c> is an integer constant.

 The reason for this change is that : on x86, conditional-move-from-constant needs two instructions;
however, conditional-move-from-register need only one instruction.

  While the LowerSELECT() sounds to be the most convenient place for this optimization, it turns out to be a bad place. The reason is that by replacing the constant <c> with a symbolic value, it obscure some instruction-combining opportunities which would otherwise be very easy to spot. For that reason, I have to postpone the change to last instruction-combining phase.

  The change passes the test of "make check-all -C <build-root/test" and "make -C project/test-suite/SingleSource".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165661 91177308-0d34-0410-b5e6-96231b3b80d8
XFAIL for all targets pending investigation

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165664 91177308-0d34-0410-b5e6-96231b3b80d8

Add a new interface to allow IR-level passes to access codegen-specific information.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165665 91177308-0d34-0410-b5e6-96231b3b80d8
Add -mattr=+altivec and remove XFAIL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165666 91177308-0d34-0410-b5e6-96231b3b80d8
Formatting and 80-col.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165668 91177308-0d34-0410-b5e6-96231b3b80d8
Remove unused member variable introduced in r165665.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165669 91177308-0d34-0410-b5e6-96231b3b80d8